JPH0178046U - - Google Patents
Info
- Publication number
- JPH0178046U JPH0178046U JP1987174096U JP17409687U JPH0178046U JP H0178046 U JPH0178046 U JP H0178046U JP 1987174096 U JP1987174096 U JP 1987174096U JP 17409687 U JP17409687 U JP 17409687U JP H0178046 U JPH0178046 U JP H0178046U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- view
- plan
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例である半導体集積
回路をプリント基板に取付けた場合の平面図、第
２図はこの考案の半導体集積回路による左右外部
端子と配線の関係を示す説明図、第３図ａ，ｂは
この考案の半導体集積回路のデユアル・インライ
ン・パツケージの平面図および正面図、第４図、
第５図は外部端子がＪ形に整形されたＳＯＪおよ
びＳＯＰ半導体集積回路のそれぞれ他の実施例を
示す平面図、第６図ａ，ｂは従来のデユアル・イ
ンライン・パツケージの半導体集積回路の平面図
および正面図、第７図は従来の半導体集積回路の
左右外部端子と配線の関係を示す説明図である。
図において、１は半導体集積回路の外部端子、
２は半導体集積回路の主面、３はプリント基板の
配線、４，５はプリント基板上の半導体集積回路
を示す。なお、図中、同一符号は同一または相当
部分を示す。
Fig. 1 is a plan view of a semiconductor integrated circuit according to an embodiment of this invention mounted on a printed circuit board; Fig. 2 is an explanatory diagram showing the relationship between left and right external terminals and wiring in the semiconductor integrated circuit of this invention; 3a and b are a plan view and a front view of the dual in-line package of the semiconductor integrated circuit of this invention, and FIG.
FIG. 5 is a plan view showing other embodiments of SOJ and SOP semiconductor integrated circuits in which external terminals are shaped into a J shape, and FIGS. 6a and 6b are plan views of conventional dual in-line package semiconductor integrated circuits. The figure, front view, and FIG. 7 are explanatory diagrams showing the relationship between left and right external terminals and wiring of a conventional semiconductor integrated circuit. In the figure, 1 is an external terminal of a semiconductor integrated circuit;
Reference numeral 2 indicates the main surface of the semiconductor integrated circuit, 3 indicates the wiring of the printed circuit board, and 4 and 5 indicate the semiconductor integrated circuits on the printed circuit board. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
を半導体集積回路の主面２に対して左右を平行に
ずらし、互いに千鳥状に配置したことを特徴とす
る半導体集積回路。 External terminal 1 derived from the semiconductor integrated circuit
A semiconductor integrated circuit characterized in that the left and right sides are shifted parallel to the main surface 2 of the semiconductor integrated circuit and are arranged in a staggered manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987174096U JPH0178046U (en) | 1987-11-12 | 1987-11-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987174096U JPH0178046U (en) | 1987-11-12 | 1987-11-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0178046U true JPH0178046U (en) | 1989-05-25 |
Family
ID=31465971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987174096U Pending JPH0178046U (en) | 1987-11-12 | 1987-11-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0178046U (en) |
-
1987
- 1987-11-12 JP JP1987174096U patent/JPH0178046U/ja active Pending
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