JPH0186256U - - Google Patents
Info
- Publication number
- JPH0186256U JPH0186256U JP18308387U JP18308387U JPH0186256U JP H0186256 U JPH0186256 U JP H0186256U JP 18308387 U JP18308387 U JP 18308387U JP 18308387 U JP18308387 U JP 18308387U JP H0186256 U JPH0186256 U JP H0186256U
- Authority
- JP
- Japan
- Prior art keywords
- operating state
- terminal
- test
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例で、ａは回路図、
ｂはモニター出力信号とテストモード選択用のゲ
ートしきい値の関係を示すタイムチヤート、第２
図は従来例の回路図、第３図は他の従来例の回路
図である。
図において１はテストモード選択用のゲート、
２はモニター出力用回路、３，４は抵抗、５はモ
ニター出力、及びテストモード選択端子である。
なお、図中、同一符号は同一、又は相当部分を示
す。
Figure 1 shows an embodiment of this invention, where a is a circuit diagram;
b is a time chart showing the relationship between the monitor output signal and the gate threshold for test mode selection;
The figure is a circuit diagram of a conventional example, and FIG. 3 is a circuit diagram of another conventional example. In the figure, 1 is a gate for test mode selection;
2 is a monitor output circuit, 3 and 4 are resistors, and 5 is a monitor output and test mode selection terminal.
In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
補正 昭６３．３．３ 考案の名称を次のように補正する。 考案の名称 半導体集積回路Correction 1986.3.3 The name of the invention is amended as follows. Name of invention: Semiconductor integrated circuit
Claims (1)
する半導体集積回路において、実動作状態時には
当該端子を電源に接続し、あるいは接地するとと
もに、試験動作状態時には当該端子を試験時監視
信号等の出力回路用として使用することを特徴と
した半導体集積回路。 In a semiconductor integrated circuit having a terminal for selecting an actual operating state and a test operating state, in the actual operating state, the terminal is connected to a power supply or grounded, and in the test operating state, the terminal is connected to an output circuit for test monitoring signals, etc. A semiconductor integrated circuit characterized by being used for various purposes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18308387U JPH0186256U (en) | 1987-11-30 | 1987-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18308387U JPH0186256U (en) | 1987-11-30 | 1987-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0186256U true JPH0186256U (en) | 1989-06-07 |
Family
ID=31474516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18308387U Pending JPH0186256U (en) | 1987-11-30 | 1987-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0186256U (en) |
-
1987
- 1987-11-30 JP JP18308387U patent/JPH0186256U/ja active Pending