JPH0187449U - - Google Patents

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Publication number
JPH0187449U
JPH0187449U JP18459287U JP18459287U JPH0187449U JP H0187449 U JPH0187449 U JP H0187449U JP 18459287 U JP18459287 U JP 18459287U JP 18459287 U JP18459287 U JP 18459287U JP H0187449 U JPH0187449 U JP H0187449U
Authority
JP
Japan
Prior art keywords
frequency dividing
circuit
dividing circuit
bus
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18459287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18459287U priority Critical patent/JPH0187449U/ja
Publication of JPH0187449U publication Critical patent/JPH0187449U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例の分周回路のブロ
ツク図、第2図は従来の分周回路のブロツク図、
第3図は基本クロツク信号および16分周信号の
波形図である。 図において、1は基本クロツクの供給点、2は
分周回路、3は各種機能回路、4は基本クロツク
信号、5は16分周後クロツク信号、6は切換ス
イツチ、7は回避バスを示す。なお、図中同一符
号は同一、または相当部分を示す。
Figure 1 is a block diagram of a frequency divider circuit according to an embodiment of this invention, Figure 2 is a block diagram of a conventional frequency divider circuit,
FIG. 3 is a waveform diagram of the basic clock signal and the 16 frequency divided signal. In the figure, 1 is a basic clock supply point, 2 is a frequency dividing circuit, 3 is various functional circuits, 4 is a basic clock signal, 5 is a clock signal after frequency division by 16, 6 is a changeover switch, and 7 is an avoidance bus. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] クロツクを分周してできた信号を同期信号とし
て動作する回路の分周回路を回避するバスと切換
機能を設けたことを特徴とするマイクロコンピユ
ータの分周回路。
A frequency dividing circuit for a microcomputer, characterized in that it is provided with a bus and a switching function to avoid the frequency dividing circuit of a circuit that operates using a signal generated by frequency dividing a clock as a synchronizing signal.
JP18459287U 1987-12-02 1987-12-02 Pending JPH0187449U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18459287U JPH0187449U (en) 1987-12-02 1987-12-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18459287U JPH0187449U (en) 1987-12-02 1987-12-02

Publications (1)

Publication Number Publication Date
JPH0187449U true JPH0187449U (en) 1989-06-09

Family

ID=31475941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18459287U Pending JPH0187449U (en) 1987-12-02 1987-12-02

Country Status (1)

Country Link
JP (1) JPH0187449U (en)

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