JPH0187543U - - Google Patents
Info
- Publication number
- JPH0187543U JPH0187543U JP18459587U JP18459587U JPH0187543U JP H0187543 U JPH0187543 U JP H0187543U JP 18459587 U JP18459587 U JP 18459587U JP 18459587 U JP18459587 U JP 18459587U JP H0187543 U JPH0187543 U JP H0187543U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- section
- decoding circuit
- reconnecting
- irregular
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例によるＲＯＭのコ
ントロール回路を示す論理図、第２図はこの考案
の一実施例によるＲＯＭのコントロール回路のパ
ターン図、第３図ａ，ｂは第２図による入力接続
部のつなぎ換えの変化を示すパターン図、第４図
ａ〜ｄは第２図による出力接続部のつなぎ換えの
変化を示すパターン図、第５図ａ〜ｄは従来の記
憶容量の違うＲＯＭのコントロール回路を示す論
理図である。
図において、６は固定論理部、７は変動論理部
、８は接続信号線、９は選択配線部、１９は入力
接続部、２０は出力接続部である。なお、図中、
同一符号は同一、又は相当部分を示す。
Fig. 1 is a logic diagram showing a ROM control circuit according to an embodiment of this invention, Fig. 2 is a pattern diagram of a ROM control circuit according to an embodiment of this invention, and Figs. 3a and b are based on Fig. 2. Pattern diagrams showing changes in connection of the input connection section, Figures 4 a to d are pattern diagrams showing changes in connection of the output connection section according to Figure 2, and Figures 5 a to d are diagrams showing differences in conventional storage capacity. FIG. 2 is a logic diagram showing a control circuit of a ROM. In the figure, 6 is a fixed logic section, 7 is a variable logic section, 8 is a connection signal line, 9 is a selection wiring section, 19 is an input connection section, and 20 is an output connection section. In addition, in the figure,
The same reference numerals indicate the same or corresponding parts.
Claims (1)
路において、入力部並びに出力部でのアルミ配線
のつなぎ換えにより上記デコード回路の類似回路
をチヤネル及び拡散面積を変えずに形成したこと
を特徴とするＭＯＳ回路。 A decoding circuit forming an irregular MOS circuit, characterized in that a circuit similar to the above decoding circuit is formed by reconnecting aluminum wiring at the input section and the output section without changing the channel and diffusion area. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18459587U JPH0187543U (en) | 1987-12-02 | 1987-12-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18459587U JPH0187543U (en) | 1987-12-02 | 1987-12-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0187543U true JPH0187543U (en) | 1989-06-09 |
Family
ID=31475944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18459587U Pending JPH0187543U (en) | 1987-12-02 | 1987-12-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0187543U (en) |
-
1987
- 1987-12-02 JP JP18459587U patent/JPH0187543U/ja active Pending