JPH0188526U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the pulse extraction circuit of the present invention, Fig. 2 is a waveform diagram showing its operation, Fig. 3 is a waveform diagram showing the operation of the pulse extraction circuit, and Fig. 4 is a waveform diagram showing the operation of the pulse extraction circuit.
The figure shows a configuration diagram and an operation waveform diagram of an example of a conventional comparator. 1, 5... Comparator, 2, 3... Pulse generation circuit, 4... AND circuit, 31, 32... Mono multi.

Claims (1)

[Scope of utility model registration request] A pulse extraction circuit that differentiates an input pulse signal, measures the pulse interval using the zero crossing point of the differentiated signal, and extracts a pulse whose interval with the previous pulse is a fixed time from a pulse train. a first comparator which receives the differential signal and whose comparison level is biased to remove the influence of noise; and a first comparator which is triggered by the output signal of the first comparator to produce the output signal. a first pulse generating circuit that generates a first window pulse having a time width that includes the timing of zero crossing in the differential signal; a second pulse generation circuit that generates a second window pulse of a certain time width after a certain period of time has elapsed; an AND circuit to which the first and second window pulses are applied; a second comparator whose operating state is controlled and which receives the differential signal and generates an output pulse signal.