JPH0193166A - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPH0193166A
JPH0193166A JP62249113A JP24911387A JPH0193166A JP H0193166 A JPH0193166 A JP H0193166A JP 62249113 A JP62249113 A JP 62249113A JP 24911387 A JP24911387 A JP 24911387A JP H0193166 A JPH0193166 A JP H0193166A
Authority
JP
Japan
Prior art keywords
layer
gaas
quantum well
doped
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62249113A
Other languages
Japanese (ja)
Other versions
JPH0376787B2 (en
Inventor
Kenichi Imamura
健一 今村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP62249113A priority Critical patent/JPH0193166A/en
Publication of JPH0193166A publication Critical patent/JPH0193166A/en
Publication of JPH0376787B2 publication Critical patent/JPH0376787B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H10D62/605—Planar doped, e.g. atomic-plane doped or delta-doped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36—Unipolar devices
    • H10D48/362—Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To reduce base resistance of a resonance tunneling hot electron transistor by a method wherein a resonance tunneling barrier is constituted of a first quantum well barrier layer, a first quantum well layer, and a second quantum well barrier layer. CONSTITUTION:An N<+>-GaAs collector layer 1 is grown on a semi-insulating GaAs substrate SI. A non-dope GaAs layer is grown 1500Angstrom thick, Be is planar- doped thereinto, and then another non-dope GaAs layer is grown 500Angstrom thick, for the formation of a collector barrier 2. An N<+> GaAs base layer 3 is grown, and then quantum well layers 4, 5, and 6 are formed. Here, the GaAs barrier layers 4 and 6 are 100Angstrom thick each and planar-doped with Be at a level half the thickness, and the non-dope layer 5 is a 100Angstrom -thick well layer. Finally, an N<+>-GaAs emitter layer 7 is grown for the completion of an epitaxial layer structure. This design reduces the resistance a base may present in a resonance tunneling hot transistor.

Description

【発明の詳細な説明】 〔概要〕 半導体に不純物を多量ドーピングするとバンド構造が影
響を受ける。プレーナドーピング(PD)と呼ばれる2
次元的局所ドーピングによって半導法(MBE法)によ
りエミッタバリアとして量子井戸を、コレクタバリアと
して一つのポテンシャルバリアが形成された。
[Detailed Description of the Invention] [Summary] When a semiconductor is doped with a large amount of impurities, the band structure is affected. 2 called planar doping (PD)
A quantum well was formed as an emitter barrier and one potential barrier was formed as a collector barrier using a semiconductor method (MBE method) by dimensional local doping.

本発明のRHETは、 AlGaAsを用いることなく
GaAsだけによる多層構成であり、良好な素子特性が
得られまた製造プロセスが単純化される。
The RHET of the present invention has a multilayer structure made only of GaAs without using AlGaAs, so that good device characteristics can be obtained and the manufacturing process can be simplified.

〔産業上の利用分野〕[Industrial application field]

本発明は共鳴トンネリングホットエレクトロントランジ
スタ(RHET)構造に関する。
The present invention relates to resonant tunneling hot electron transistor (RHET) structures.

RHETは最近に超格子構造を応用して生まれた新しい
デバイスである。該デバイスは共鳴トンネリング効果を
利用し、高いエネルギを持つホットエレクトロンの動き
を制御できるので、高速の論理、記憶などの機能を持つ
どとができる。
RHET is a new device recently created by applying a superlattice structure. This device utilizes the resonant tunneling effect and can control the movement of high-energy hot electrons, allowing it to have functions such as high-speed logic and memory.

更にまた最少数のデバイスによりLSIを構成する回路
機−を実現できるものとして期待されている。
Furthermore, it is expected that a circuit device constituting an LSI can be realized using a minimum number of devices.

RHETは現在まだ研究開発途上にあり、結晶材料、素
子構造5回路設計の研究が活発に進められている (従来の技術〕 RHETは従来必ず化合物半導体のへテロ接合を有し、
 GaAs/AlGaAs 、GaAs/AlGaAs
  などはその例である。第3図は従来のRHETの構
造を示したものである。本例においては、半絶縁性Ga
As基板(S、1. GaAs)の上に例えば2MbE
法により順次n”−GaAsコレクタ層11. AlG
aAsバリア層12.n−GaAsベース層13を形成
し、更にAlGaAs層14゜GaAsW!i 15+
 AlGaAs層16の量子井戸層とn” GaAsエ
ミッタ層17を形成する。
RHET is currently still in the research and development stage, and research on crystal materials and element structure 5 circuit design is actively progressing (Conventional technology) RHET has conventionally always had a compound semiconductor heterojunction;
GaAs/AlGaAs, GaAs/AlGaAs
are examples. FIG. 3 shows the structure of a conventional RHET. In this example, semi-insulating Ga
For example, 2MbE on an As substrate (S, 1.GaAs)
The n”-GaAs collector layer 11.AlG
aAs barrier layer 12. An n-GaAs base layer 13 is formed, and an AlGaAs layer 14°GaAsW! i 15+
A quantum well layer of AlGaAs layer 16 and an n'' GaAs emitter layer 17 are formed.

上記各層の諸元は例えば次の通りである。For example, the specifications of each layer are as follows.

図番   エピタキシャル  濃度   厚さ層、  
     (Cm””)   (人)11      
   n+ −GaA’s          5xl
O”     300012  Alx Ga1−xA
s(x=0.2)  ノンドープ 200013   
  n” −GaAs     1xlO”   50
014  AlxGa、−xAs(x=0.3)  ノ
ンドープ  5015      GaAs    ノ
ンドープ 5016  AlGaAs■As(x=0.
3)  ノンドープ  5017     n”−Ga
As     5xlO”   20001部50 エミッタ17. ベース13.コレクタ11各層には金
・ゲルマニウム/金(AuGe/Au)電極が取り付け
られる。
Drawing number Epitaxial concentration Thickness layer,
(Cm””) (person) 11
n+ -GaA's 5xl
O” 300012 Alx Ga1-xA
s (x=0.2) Non-doped 200013
n"-GaAs 1xlO" 50
014 AlxGa, -xAs (x=0.3) Non-doped 5015 GaAs Non-doped 5016 AlGaAs■As (x=0.
3) Non-doped 5017 n”-Ga
As 5xlO" 20001 Part 50 Emitter 17. Base 13. Collector 11 Gold/germanium/gold (AuGe/Au) electrodes are attached to each layer.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来例からも明らかなように、RHETはGaAsとA
lGaAsとのへテロ接合により構成される。従ってデ
バイスプロセス及びエピタキシャル成長プロセスはヘテ
ロ接合を含まない例えばGaAsのみからなるプロセス
に比較して一般に複雑にならざるを得ない。
As is clear from the conventional example, RHET is made of GaAs and A
It is composed of a heterojunction with lGaAs. Therefore, device processes and epitaxial growth processes generally have to be more complicated than processes that do not include a heterojunction and are made only of GaAs, for example.

〔問題点を解決するための手段〕[Means for solving problems]

このような問題点は、半絶縁性基板上にn型ガリ′ウム
砒素(GaAs)からなるコレクタ層、ベリリウム(B
e)がプレーナドープされたガリウム砒素からなるコレ
クタバリア層、n型ガリウム砒素からなるベース層、ベ
リリウムがプレーナドープされたガリウム砒素からなる
第1の量子井戸バリア層、ガリウム砒素からなる量子井
戸ウェル層、ベリリウムがプレーナドープされたガリウ
ム砒素からなる第2の量子井戸バリア層、n型ガリウム
砒素からなるエミッタ層が形成され、該第1の量子井戸
バリア層と量子井戸ウェル層と第2の量子井戸バリア層
が共鳴・トンネリングバリア構成となることを特徴とす
るR)(ETによって解決される。
These problems can be solved by using a collector layer made of n-type gallium arsenide (GaAs) and beryllium (B) on a semi-insulating substrate.
e) is a collector barrier layer made of planar-doped gallium arsenide, a base layer made of n-type gallium arsenide, a first quantum well barrier layer made of gallium arsenide planar-doped with beryllium, and a quantum well well layer made of gallium arsenide. , a second quantum well barrier layer made of gallium arsenide planar-doped with beryllium, and an emitter layer made of n-type gallium arsenide are formed, and the first quantum well barrier layer, the quantum well well layer, and the second quantum well are formed. R) characterized in that the barrier layer has a resonance/tunneling barrier configuration (solved by ET).

〔作用〕[Effect]

第2図は本発明によるプレーナドープRHETのバンド
構造図で特に伝導帯底(Ec)を示したものである。
FIG. 2 is a band structure diagram of the planar-doped RHET according to the present invention, particularly showing the conduction band bottom (Ec).

プレーナドーピングと呼ばれるものは、MBE法におい
てエピタキシャル成長を一時停止させ。
What is called planar doping temporarily halts epitaxial growth in the MBE method.

その状態でドーパントのみを供給しその後再び成長を開
始する手法である。GaAsM B Eの場合を例にと
れば、 Gaビームの供給中断により成長を中断し、^
S雰囲気のもとてn型ドーパントとしてはシリコン(S
i)、p型ドーパントとしてはベリリウム(Be)を供
給する。その後成長を再開する。
This is a method in which only the dopant is supplied in this state and then growth starts again. Taking the case of GaAsMBE as an example, if the supply of Ga beam is interrupted, the growth is interrupted.
Silicon (S) is used as an n-type dopant in an S atmosphere.
i) Beryllium (Be) is supplied as the p-type dopant. Then growth resumes.

GaAsへのプレーナドーピングではドーパントの拡散
は40人以内に抑制され9面濃度は最高5xlOl2c
m””まで可能である。
In planar doping of GaAs, the dopant diffusion is suppressed to within 40%, and the 9-plane concentration is up to 5xlOl2c.
m"" is possible.

n型GaAs?、:Beをプレーナドーピングすると伝
導帯底(Ec)に0.4eV程度の突起が生じこれがポ
テンシャルバリアとなる。エミッタに二つのバリアで量
子井戸を形成して第一共鳴準位(E、)を0.2eV程
度に設定することができる。このようにコレクタに一つ
のバリアを、エミッタに一つの量子井戸を形成すれば、
プレーナドープRHET構造が出来上がる。
n-type GaAs? , :Be planar doping produces a protrusion of about 0.4 eV at the conduction band bottom (Ec), which becomes a potential barrier. By forming a quantum well with two barriers in the emitter, the first resonance level (E,) can be set to about 0.2 eV. If we form one barrier in the collector and one quantum well in the emitter in this way,
A planar doped RHET structure is completed.

本発明における素子特性上の大きい改良はベース抵抗の
低減である。従来例は第3図に示されるようにベース電
極は、共鳴トンネリングバリア14、15.i6上のn
型GaAs層17を約50人残してこの上に形成される
。実験の結果によれば、金・ゲルマニウム/金(200
人/2800人)の金属膜を、厚さが30人のノンドー
プ゛AlGaAsと同じく厚さが30人のノンドープG
aAsに蒸着して、450℃において1分間熱処理を行
った場合のコンタクト抵抗率は、前者が約2.0x10
−5ΩC1112に対して後者は2.0xlO−’Ωc
ffI2である。この結果からもわかるようにGaAs
のみによって構成される本発明によるR HE Tのベ
ース抵抗は従来例に比較して1桁低減される。
A major improvement in device characteristics in the present invention is a reduction in base resistance. In the conventional example, as shown in FIG. 3, the base electrode has resonant tunneling barriers 14, 15 . n on i6
A type GaAs layer 17 is formed on this, leaving about 50 layers. According to the experimental results, gold/germanium/gold (200
A metal film with a thickness of 30 people/2800 people is made of non-doped AlGaAs with a thickness of 30 people, and a non-doped G film with a thickness of 30 people
When deposited on aAs and heat treated at 450°C for 1 minute, the contact resistivity of the former is approximately 2.0x10
-5ΩC1112, the latter is 2.0xlO-'Ωc
It is ffI2. As can be seen from this result, GaAs
The base resistance of the R HE T according to the present invention, which is constructed solely by the present invention, is reduced by one order of magnitude compared to the conventional example.

〔実施例〕〔Example〕

第1図は本発明によるプレーナドープRHETの断面構
造模式図である。
FIG. 1 is a schematic cross-sectional structural diagram of a planar-doped RHET according to the present invention.

半絶縁性GaAs基板(5,1,GaAs)の上にMB
E法によりまずn”−GaAsコレクタ層1を成長させ
。
MB on a semi-insulating GaAs substrate (5,1,GaAs)
First, an n''-GaAs collector layer 1 was grown using the E method.

次ぎにノンドープGaAsNを1500人だけさせた後
に、 BeをプレーナドープしてまたノンドープGaA
sを500人成長させてコレクタバリア層2を形成する
。次いでn”−GaAsベース層3を成長させて後量子
井戸層4,5.6を形成する。即ちGaAsバリア層4
.6はいずれも厚さが100人で、半分の厚さの位置に
おいてBeプレーナドープされている。ノンドープGa
As層5は厚さが100 人のウェル層である。
Next, after making only 1500 non-doped GaAsN, Be was doped planarly and non-doped GaAs was added again.
A collector barrier layer 2 is formed by growing 500 layers of s. Next, the n''-GaAs base layer 3 is grown to form the post-quantum well layers 4, 5.6. That is, the GaAs barrier layer 4
.. No. 6 has a thickness of 100 μm and is doped with Be planar at half the thickness. Non-doped Ga
The As layer 5 is a well layer with a thickness of 100 .mu.m.

最後にn”−GaAsエミフタ層7を成長させてエピタ
キシャル層構造が完成される。
Finally, an n''-GaAs emitter layer 7 is grown to complete the epitaxial layer structure.

図中、プレーナドープ面の位置を点線によって示した。In the figure, the position of the planar doped surface is indicated by a dotted line.

エミッタ層7.ベースN3.コレクタ層1にはいずれも
金・ゲルマニウム(200人)/金(3000人) (
AuGe上記各エピタキシャル層の主要諸元をまとめて
次に示す。
Emitter layer 7. Base N3. Collector layer 1 includes gold/germanium (200 people) / gold (3000 people) (
The main specifications of each of the above-mentioned AuGe epitaxial layers are summarized below.

図番  エピタキシャル  濃度  厚さJi    
  (cm−’)   (人)1     n ” −
GaAs   5xlO”   30002     
  GaAs  ノンドープ 1500PD :Be 
 1xlO”cm−2 GaAs  ノンドープ 500 3     n ” −GaAs   1xlO”  
 5004       GaAs  ノンドープ  
50PD ;Be  1xlOl2cm−2GaAs 
 ノンドープ  50 5       GaAs  ノンドープ 1005 
      GaAs  ノンドープ  50PD  
二Be   1xlO”cm−2GaAs  ノンドー
プ  50 〔発明の効果〕 従来のRHE Tには必ず化合物半導体のへ手口接合が
含まれる。このために該素子製造におけるエピタキシャ
ル成長工程、デバイスプロセス工程が複雑にならざるを
得ない。
Drawing number Epitaxial concentration Thickness Ji
(cm-') (person) 1 n''-
GaAs 5xlO” 30002
GaAs non-doped 1500PD:Be
1xlO"cm-2 GaAs Non-doped 500 3 n" -GaAs 1xlO"
5004 GaAs non-doped
50PD ; Be 1xlOl2cm-2GaAs
Non-doped 50 5 GaAs Non-doped 1005
GaAs non-doped 50PD
2Be 1xlO"cm-2GaAs Non-doped 50 [Effects of the Invention] Conventional RHE T always includes a hemijunction of a compound semiconductor. For this reason, the epitaxial growth process and device process process in manufacturing the element become complicated. I don't get it.

本発明によるRHETはへテロ接合を一切利用せずホモ
接合のみで構成される故に、従来の素子製造工程は簡素
化され、従って該素子の低コスト化にも寄与するところ
大である。
Since the RHET according to the present invention does not utilize any heterojunctions and is composed of only homojunctions, the conventional device manufacturing process is simplified, which greatly contributes to lowering the cost of the device.

また素子のベース抵抗については、 /1IGaAsを
全く含まない本発明のRHETでは従来のRHE Tに
比べて10分の1に低減された。これは高速素子として
のRHET開発における進歩である。
Furthermore, the base resistance of the element was reduced to one-tenth of that of the conventional RHET in the RHET of the present invention, which does not contain any /1I GaAs. This is an advance in the development of RHET as a high speed device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるプレーナドープRHE i’の断
面構造模式図。 第2図は本発明によるプレーナドープRHE Tのエネ
ルギバンド構造図。 第3図は従来のRHE Tの断面構造模式図である。 図において。 1はn”−GaAsコレクタ層。 2はGaAsコレクタバリア層。 3はn”−GaAsベース層。 4.5.6はGaAs量子井戸層。 7はn”−GaAsエミッタ層 である。 特許出願人 工業技術院長 飯塚幸三 1    N6aAsコしりl7ii 2   (mAs:ILりl7tZす7層3   N6
aA5 、(−7厘 4   qaAs 署し了杵戸l;す?眉5  Gra
k t−)好”+zcJi6    ff1aAs  
I)tFp+r’J?眉7   lσ’(raA5 工
、ミ、リタ屈a症すイし一作一っ0面 本雄朔によるR1−11m丁断面構造、膿太・匣第 1
1!1 木襲A嘱tてJろR)−1εTLネルへ゛/S’シμ゛
横!L条 2 @ 従粟のi+qTり新1構亀膿式′圀 第  ろ  ■
FIG. 1 is a schematic cross-sectional structural diagram of a planar-doped RHE i' according to the present invention. FIG. 2 is an energy band structure diagram of a planar-doped RHET according to the present invention. FIG. 3 is a schematic cross-sectional structural diagram of a conventional RHET. In fig. 1 is an n''-GaAs collector layer. 2 is a GaAs collector barrier layer. 3 is an n''-GaAs base layer. 4.5.6 is a GaAs quantum well layer. 7 is an n''-GaAs emitter layer. Patent applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka 1 N6aAs layer 7ii 2 (mAs: IL layer 7 layer 3 N6
aA5 , (-7厘4 qaAs Signed to complete; Su? Eyebrow 5 Gra
k t-)Good”+zcJi6 ff1aAs
I) tFp+r'J? Eyebrow 7 lσ' (raA5 Engineering, Mi, Rita Kakusui Suishi Issaku 10th page R1-11m section structure by Yusaku Moto, Yuta・Hako No. 1
1! 1 Wood attack A start JroR)-1εTL channel ゛/S'shiμ゛side! L article 2 @ Juso's i + qT Rishin 1 structure Kamepus style'Kokudairo ■

Claims (1)

【特許請求の範囲】[Claims]  半絶縁性基板上にn型ガリウム砒素(GaAs)から
なるコレクタ層、ベリリウム(Be)がプレーナドープ
されたガリウム砒素からなるコレクタバリア層、n型ガ
リウム砒素からなるベース層、ベリリウムがプレーナド
ープされたガリウム砒素からなる第1の量子井戸バリア
層、ガリウム砒素からなる量子井戸ウェル層、ベリリウ
ムがプレーナドープされたガリウム砒素からなる第2の
量子井戸バリア層、n型ガリウム砒素からなるエミッタ
層が形成され、該第1の量子井戸バリア層と量子井戸ウ
ェル層と第2の量子井戸バリア層が共鳴トンネリングバ
リア構成となることを特徴とする半導体装置。
A collector layer made of n-type gallium arsenide (GaAs) on a semi-insulating substrate, a collector barrier layer made of gallium arsenide planar-doped with beryllium (Be), a base layer made of n-type gallium arsenide, and a beryllium-doped base layer. A first quantum well barrier layer made of gallium arsenide, a quantum well well layer made of gallium arsenide, a second quantum well barrier layer made of gallium arsenide planar-doped with beryllium, and an emitter layer made of n-type gallium arsenide are formed. . A semiconductor device, wherein the first quantum well barrier layer, the quantum well well layer, and the second quantum well barrier layer have a resonant tunneling barrier configuration.
JP62249113A 1987-10-03 1987-10-03 semiconductor equipment Granted JPH0193166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62249113A JPH0193166A (en) 1987-10-03 1987-10-03 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62249113A JPH0193166A (en) 1987-10-03 1987-10-03 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPH0193166A true JPH0193166A (en) 1989-04-12
JPH0376787B2 JPH0376787B2 (en) 1991-12-06

Family

ID=17188146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62249113A Granted JPH0193166A (en) 1987-10-03 1987-10-03 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPH0193166A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278427A (en) * 1993-02-04 1994-01-11 The United States Of America As Represented By The Secretary Of The Army Quantum collector hot-electron transistor
US5389798A (en) * 1991-10-02 1995-02-14 Mitsubishi Denki Kabushiki Kaisha High-speed semiconductor device with graded collector barrier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5389798A (en) * 1991-10-02 1995-02-14 Mitsubishi Denki Kabushiki Kaisha High-speed semiconductor device with graded collector barrier
US5278427A (en) * 1993-02-04 1994-01-11 The United States Of America As Represented By The Secretary Of The Army Quantum collector hot-electron transistor

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