JPH0193227A - Signaling inserting circuit - Google Patents

Signaling inserting circuit

Info

Publication number
JPH0193227A
JPH0193227A JP25098287A JP25098287A JPH0193227A JP H0193227 A JPH0193227 A JP H0193227A JP 25098287 A JP25098287 A JP 25098287A JP 25098287 A JP25098287 A JP 25098287A JP H0193227 A JPH0193227 A JP H0193227A
Authority
JP
Japan
Prior art keywords
bit
signal
signaling information
bits
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25098287A
Other languages
Japanese (ja)
Inventor
Takeshi Miyazaki
剛 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25098287A priority Critical patent/JPH0193227A/en
Publication of JPH0193227A publication Critical patent/JPH0193227A/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To improve deterioration in the quality of a voice signal by substituting a digital signal of prescribed bits in inputted digital signals of N bits for signaling information which detects the change point of a dial pulse, and sending a PCM signal of prescribed bits for the information other than that. CONSTITUTION:The dial pulse and a sampling pulse are added on the D terminal and the CK terminal of a D-FF11, and the exclusive OR of the output and the one in which the output is shifted by one bit via a D-FF21 is taken at an EX-OR gate 22, and the 8th bit of the voice signal is replaced by the signaling information from the D-FF11, then, it is sent via an FF of 8 bits. Also, while no output from the EX-OR gate is issued, the 8th bit of a voice PCM signal is sent out via an FF13. In such a way, since it is possible to perform the transmission of the signaling information at speed 1/100 the on-going speed, the part of the voice PCM signal of 8 bits is increased, thereby, the deterioration in the quality of the voice signal can be improved.

Description

【発明の詳細な説明】 〔概要〕 例えば、音声信号処理装置に使用されるシグナリング挿
入回路に関し、 シグナリン多゛情報を音声PCM信号に挿入することに
よって生ずる音声信号の品質劣化の改善を目的とし、 入力するシグナリング情報の変化点を検出する変化点検
出手段と、該変化点検出手段の出力を用いて、入力する
Nビットのディジタル信号の内の所定ビットのディジタ
ル信号を該シグナリング情報に置換するシグナリング情
報置換手段とを有する様に構成する。
[Detailed Description of the Invention] [Summary] For example, with respect to a signaling insertion circuit used in an audio signal processing device, the present invention aims to improve the quality deterioration of an audio signal caused by inserting signaling multi-information into an audio PCM signal. Signaling that includes a change point detection means for detecting a change point of input signaling information, and a change point detection means that uses the output of the change point detection means to replace a predetermined bit digital signal of an input N-bit digital signal with the signaling information. and information replacement means.

〔産業上の利用分野〕[Industrial application field]

本発明は2例えば音声信号処理装置に使用されるシグナ
リング挿入回路に関するものである。
The present invention relates to a signaling insertion circuit used, for example, in an audio signal processing device.

音声信号処理装置は音声信号をPCM信号に変換する過
程において、電話のシグナリング情報(ダイヤルパルス
)等を上記のPCM信号に挿入して伝送しているが、こ
の時、音声信号の品質劣化をできるだけ少なくする様に
シグナリング情報を挿入することが必要である。
In the process of converting an audio signal into a PCM signal, the audio signal processing device inserts telephone signaling information (dial pulses) etc. into the above PCM signal and transmits it. It is necessary to insert signaling information so as to reduce the number of signals.

〔従来の技術〕[Conventional technology]

第4図はPCM信号のフレーム構成図、第5図は従来例
のブロック図、第6図は第5図の動作説明図を示す。
FIG. 4 is a frame configuration diagram of a PCM signal, FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG.

先ず、近年は種々の機能を持ったLSIが開発され、実
用化されているが、その中に単一チャンネル符号化器の
LSIがある。
First, in recent years, LSIs with various functions have been developed and put into practical use, and among them is a single channel encoder LSI.

この単一チャンネル符号化器(以下、符号化器と省略し
7図示せず)は送信側における標本化。
This single channel encoder (hereinafter abbreviated as encoder 7, not shown) performs sampling on the transmitting side.

量子化、符号化及び受信側における複合化、補間濾波を
1チツプのLSIで実現したもので、送信側では音声信
号が入力すると、第4図のワード構成に示す様に8ビツ
トの音声PCM信号が出力される様になっているが、多
重化しやすい様に送出のタイミングはずれている。
Quantization, encoding, decoding, and interpolation filtering on the receiving side are realized on a single LSI chip.When an audio signal is input on the transmitting side, it is converted into an 8-bit audio PCM signal as shown in the word structure in Figure 4. is output, but the timing of transmission is staggered to facilitate multiplexing.

そこで、この音声PCM信号は8ビツトずつ1例えば2
4チャンネル分まとめて多重化された後、この多重化パ
ルスの先頭に1ビツト (Fばットと云う)を付加して
送出するが、この時の伝送速度は1.544 Mb/s
となる。この多重化時の最小単位がフレームであるが(
第4図のフレーム構成参照)、このフレームが9例えば
24回繰り返されると付加されたFビットの使い方が一
巡し、これをマルチフレームと云う。
Therefore, this audio PCM signal is divided into 8 bits at a time, for example, 2 bits each.
After four channels are multiplexed together, one bit (called F bit) is added to the beginning of this multiplexed pulse and sent out, and the transmission rate at this time is 1.544 Mb/s.
becomes. The minimum unit during this multiplexing is a frame (
(Refer to the frame structure in FIG. 4), when this frame is repeated 9, for example, 24 times, the usage of the added F bit completes, and this is called a multi-frame.

尚、例えば第6.12.18.24フレーム(信号用フ
レームと云う)の各チャンネルの8ビツト目をシグナリ
ング情報用ビットSに置き換えて伝送するので、この信
号用フレームでは音声信号は7ビツトとなる。
For example, in the 6.12.18.24 frame (referred to as the signal frame), the 8th bit of each channel is replaced with the signaling information bit S, so in this signal frame, the audio signal is 7 bits. Become.

次に、第5図の左側の入力端子INに上記の符号化器か
らの8ビツトの音声PCM信号が加えられ、Dタイプフ
リップフロップ(以下、 D−FFと省略する)11の
D端子に第6図−〇に示すダイヤルパルスが、D−FF
 11のCK端子に第6図−■に示す9例えばI KH
z程度のサンプリングパルス(立上り点のみを示す)が
それぞれ加えられる。
Next, the 8-bit audio PCM signal from the encoder described above is applied to the input terminal IN on the left side of FIG. The dial pulse shown in Figure 6-〇 is the D-FF
For example, I KH shown in Figure 6-■ to the CK terminal of 11
A sampling pulse of order z (only the rising point is shown) is applied respectively.

そこで、D−FF 11のQ端子から1例えば00・・
111・・のシグナリング情報が出力されるが、セレク
タ12がこの時9点線側を選択しているので音声PCM
信号の8ビツト目のパルス(最下位ビット)の代りに、
このシグナリング情報がFF13に加えられ、FF 1
3から7ビツトの音声PCM信号と1ビツトのシグナリ
ング情報で構成されたPCM信号が送出される。
Therefore, from the Q terminal of D-FF 11, 1, for example 00...
The signaling information of 111... is output, but since the selector 12 has selected the 9-dotted line side at this time, the audio PCM
Instead of the 8th bit pulse (least significant bit) of the signal,
This signaling information is added to FF13, and FF1
A PCM signal consisting of a 3- to 7-bit audio PCM signal and 1-bit signaling information is transmitted.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ここで、上記の様にl [lz程度のサンプリングクロ
ックでダイヤルパルスをサンプリングして。
Here, as described above, sample the dial pulse with a sampling clock of about l[lz.

音声PCM信号の8ビツト目と置き換えるが、この時、
音声信号としては7ビツトで符号化されたごとになって
、音声信号の品質が劣化すると云う問題点がある。
It is replaced with the 8th bit of the audio PCM signal, but at this time,
There is a problem in that the quality of the audio signal deteriorates every time the audio signal is encoded with 7 bits.

〔問題点を解決する為の手段〕[Means for solving problems]

第1図は本発明の原理ブロック図を示す。 FIG. 1 shows a block diagram of the principle of the present invention.

図中、2は入力するシグナリング情報の変化点を検出す
る変化点検出手段で、1は該変化点検出手段の出力を用
いて、入力するNビットのディジタル信号の内の所定ビ
ットのディジタル信号を該シグナリング情報に置換する
シグナリング情報置換手段である。
In the figure, 2 is a change point detecting means for detecting a change point of input signaling information, and 1 is a change point detecting means for detecting a change point of input signaling information, and 1 is a change point detecting means for detecting a predetermined bit of a digital signal of an input N-bit digital signal using the output of the change point detecting means. This is a signaling information replacement means that replaces the signaling information with the signaling information.

〔作用〕[Effect]

本発明はダイヤルパルスの波形は変化点が少なく、論理
がHレベルの状態、又はLレベルの状態に固定されてい
る時間が長い。
In the present invention, the waveform of the dial pulse has few changing points, and the logic is fixed at an H level state or an L level state for a long time.

そこで、変化点検出手段2でダイヤルパルスのソトのデ
ィジタル信号の内の所定ビットのディジタル信号と置換
するが、それ以外は所定ビットのPCM信号を送出する
様にした。これにより、音声信号の品質の劣化が改善さ
れる。
Therefore, the changing point detection means 2 replaces the digital signal of the dial pulse with a digital signal of a predetermined bit, but otherwise sends a PCM signal of a predetermined bit. This improves the quality deterioration of the audio signal.

〔実施例〕〔Example〕

第2図は本発明の実施例のブロック図、第3図1の構成
部分、D−FF 2L排他的論理和ゲート22は変化点
検出手段2の構成部分を示す。尚、第3図中の左側の符
号は第2図中の同じ符号の部分の波形を示す。又、全図
を通じて同一符号は同一対象物を示す。
FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 shows the components shown in FIG. Note that the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG. Also, the same reference numerals indicate the same objects throughout the figures.

以下、第3図を参照しながら第2図の動作を説明する。The operation shown in FIG. 2 will be explained below with reference to FIG.

す)がD−FF 11のD端子及びCK端子に加えられ
るので、Q端子からサンプリングパルスの立上り点にお
けるダイヤルパルスの状態1例えば0011・・が出力
される。
) is applied to the D terminal and CK terminal of the D-FF 11, so the state 1 of the dial pulse at the rising point of the sampling pulse, for example 0011, is output from the Q terminal.

そして、このD−FF 11の出力と、この出力を更に
D−FF 21を通して1ビツトシフトしたものとの排
他的論理和(以下、EX−ORと省略する)をEX−O
Rゲート22で取るとダイヤルパルスの変化点で1の出
力が得られる。そこで、この出力でセレクタ12を駆動
して音声PCM信号の8ビ・ノド目をD−FFIIから
のシグナリング情報で置換して8ビ・ノドのFFを介し
て送出する。尚、EX−ORゲートからの出力が送出さ
れない間は音声PCM信号の8ビツト目がFF13を介
して送出される。
Then, the exclusive OR (hereinafter abbreviated as EX-OR) of the output of this D-FF 11 and this output further shifted by 1 bit through the D-FF 21 is calculated as EX-O.
When taken by the R gate 22, an output of 1 is obtained at the change point of the dial pulse. Therefore, this output drives the selector 12 to replace the 8th bit node of the audio PCM signal with the signaling information from the D-FFII and send it out via the 8 bit node FF. Note that while the output from the EX-OR gate is not sent out, the 8th bit of the audio PCM signal is sent out via the FF 13.

即ち、従来の約100分の1程度の伝送速度でシグナリ
ング情報の伝送が可能となるので、8ビツトの音声PC
M信号の部分が増加して音声信号の品質の劣化が改善さ
れる。
In other words, it is possible to transmit signaling information at about 1/100th the transmission speed of the conventional one, so 8-bit voice PC
The M signal portion is increased, and the quality deterioration of the audio signal is improved.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明した様に本発明によれば音声信号の品質
の劣化が改善される。
As described above in detail, according to the present invention, deterioration in quality of audio signals is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理ブロック図、 第2図は本発明の実施例のブロック図、第3図は第2図
の動作説明図、 第4図はフレーム構成図、 第5図は従来例のブロック図、 第6図は第5図の動作説明図を示す。 変rcA       ’lイこ虫・ め7 図 I)重η作 シL日月 ト4第 3 起 7し一ム情−仄起 岱   ノ   − F/kbpsフロ・ノク イ芝表例め7゛ロツク 第 5  日 第5図の動丁γ晩明日
Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is a frame configuration diagram, and Fig. 5 is a conventional example. A block diagram of FIG. 6 is an explanatory diagram of the operation of FIG. Change rcA'l Ikomushi Me7 Figure I) Heavy η production ShiL Sun Moon To 4th 3rd generation 7th story - 滄き岱ノ - F/kbps Flow Nokui Shiba Table Example 7th Rock 5th Figure 5 movement γ evening tomorrow

Claims (1)

【特許請求の範囲】 入力するシグナリング情報の変化点を検出する変化点検
出手段(2)と、 該変化点検出手段(2)の出力を用いて、入力するNビ
ット(Nは正の整数)のディジタル信号の内の所定ビッ
トのディジタル信号を該シグナリング情報に置換するシ
グナリング情報置換手段(1)とを有することを特徴と
するシグナリング挿入回路。
[Claims] Change point detection means (2) for detecting change points of input signaling information; and N bits (N is a positive integer) to be input using the output of the change point detection means (2). 1. A signaling insertion circuit comprising: signaling information replacement means (1) for replacing a predetermined bit of a digital signal of a digital signal with the signaling information.
JP25098287A 1987-10-05 1987-10-05 Signaling inserting circuit Pending JPH0193227A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25098287A JPH0193227A (en) 1987-10-05 1987-10-05 Signaling inserting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25098287A JPH0193227A (en) 1987-10-05 1987-10-05 Signaling inserting circuit

Publications (1)

Publication Number Publication Date
JPH0193227A true JPH0193227A (en) 1989-04-12

Family

ID=17215915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25098287A Pending JPH0193227A (en) 1987-10-05 1987-10-05 Signaling inserting circuit

Country Status (1)

Country Link
JP (1) JPH0193227A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043213A (en) * 1989-03-20 1991-08-27 Mitsubishi Denki Kabushiki Kaisha Magnetic disk
JP2008202285A (en) * 2007-02-19 2008-09-04 Masae Suzuki Weeding implement for water way

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043213A (en) * 1989-03-20 1991-08-27 Mitsubishi Denki Kabushiki Kaisha Magnetic disk
JP2008202285A (en) * 2007-02-19 2008-09-04 Masae Suzuki Weeding implement for water way

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