JPH0193877U - - Google Patents
Info
- Publication number
- JPH0193877U JPH0193877U JP18871587U JP18871587U JPH0193877U JP H0193877 U JPH0193877 U JP H0193877U JP 18871587 U JP18871587 U JP 18871587U JP 18871587 U JP18871587 U JP 18871587U JP H0193877 U JPH0193877 U JP H0193877U
- Authority
- JP
- Japan
- Prior art keywords
- clamp
- circuit
- output
- input
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013256 coordination polymer Substances 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
- Studio Circuits (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は第１図の動作を示す波形図、第３図は従来例
のブロツク図である。
１……映像入力端子、２……同期信号分離回路
、３……クランプ回路、４……ＣＰ発生回路、５
……Ｈ．ＢＬＫ発生回路、６……９ＨＶＤ発生回
路、７……ＡＮＤゲート、８……出力端子。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a waveform diagram showing the operation of FIG. 1, and FIG. 3 is a block diagram of a conventional example. 1... Video input terminal, 2... Synchronous signal separation circuit, 3... Clamp circuit, 4... CP generation circuit, 5
...H. BLK generation circuit, 6...9HVD generation circuit, 7...AND gate, 8...output terminal.
Claims (1)
ンプ回路とに信号を受け、同期信号分離回路の出
力をクランプパルス発生回路と水平ブランキング
パルス発生回路と９Ｈ垂直ドライブパルス発生回
路とに受け、クランプパルス（以下ＣＰと記す）
と水平ブランキングパルス（以下Ｈ．ＢＬＫと記
す）と９Ｈ垂直ドライブ（以下ＶＤと記す）パル
スをＡＮＤゲートに入力し、その出力をＣＰとし
て前記クランプ回路へ入力し、このクランプ回路
出力を出力端子へ受けるように構成したことを特
徴とするクランプ装置。 A signal is received from the video signal input terminal to a synchronization signal separation circuit and a clamp circuit, and the output of the synchronization signal separation circuit is received to a clamp pulse generation circuit, a horizontal blanking pulse generation circuit, and a 9H vertical drive pulse generation circuit, and a clamp pulse ( (hereinafter referred to as CP)
, a horizontal blanking pulse (hereinafter referred to as H.BLK), and a 9H vertical drive (hereinafter referred to as VD) pulse are input to the AND gate, and the output is input to the clamp circuit as CP, and this clamp circuit output is input to the output terminal. A clamp device characterized in that it is configured to be received by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18871587U JPH0193877U (en) | 1987-12-10 | 1987-12-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18871587U JPH0193877U (en) | 1987-12-10 | 1987-12-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0193877U true JPH0193877U (en) | 1989-06-20 |
Family
ID=31479788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18871587U Pending JPH0193877U (en) | 1987-12-10 | 1987-12-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0193877U (en) |
-
1987
- 1987-12-10 JP JP18871587U patent/JPH0193877U/ja active Pending
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