JPH0193884U - - Google Patents
Info
- Publication number
- JPH0193884U JPH0193884U JP1987189089U JP18908987U JPH0193884U JP H0193884 U JPH0193884 U JP H0193884U JP 1987189089 U JP1987189089 U JP 1987189089U JP 18908987 U JP18908987 U JP 18908987U JP H0193884 U JPH0193884 U JP H0193884U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- gain control
- signal
- input terminal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Picture Signal Circuits (AREA)
- Television Receiver Circuits (AREA)
Description
第１図は本考案になるＡＧＣ回路の一実施例の
ブロツク図、第２図はＧＣ回路の一例を示す回路
図、第３図は制御信号の電圧対利得の関係を示す
図、第４図は利得対ノイズレベルの関係を示す図
、第５図は従来のＡＧＣ回路のブロツク図である
。
１……固体撮像素子、２……利得制御（ＧＣ）
回路、２ａ……第１入力端子、２ｂ……出力端子
、２ｃ……第２入力端子、２ｄ……制御端子、３
……１Ｈデイレイライン、４……検出回路、５…
…加算器、６……減算器、７，８……定電流源、
Ｑ１〜Ｑ６……ＮＰＮトランジスタ、Ｒ１〜Ｒ７
……抵抗。
Fig. 1 is a block diagram of one embodiment of the AGC circuit according to the present invention, Fig. 2 is a circuit diagram showing an example of the GC circuit, Fig. 3 is a diagram showing the relationship between voltage and gain of the control signal, and Fig. 4 is a diagram showing the relationship between gain and noise level, and FIG. 5 is a block diagram of a conventional AGC circuit. 1... Solid-state image sensor, 2... Gain control (GC)
Circuit, 2a...first input terminal, 2b...output terminal, 2c...second input terminal, 2d...control terminal, 3
...1H delay line, 4...detection circuit, 5...
... Adder, 6 ... Subtractor, 7, 8 ... Constant current source,
Q1 to Q6 ...NPN transistor, R1 to R7
……resistance.
Claims (1)
る利得制御回路と、 この利得制御回路の出力信号から制御信号を生
成し前記利得制御回路に供給する検波回路と、 前記利得制御回路の出力信号を１水平走査期間
遅延させ、その信号を前記利得制御回路の第２の
入力端子に供給する遅延回路とより構成し、 前記利得御回路は前記制御信号に応じて、前記
第１の入力端子に入来する信号に対する利得をＸ
倍からＹ倍（Ｘ＜Ｙ）に変化させると共に、前記
第２の入力端子に入来する信号に対する利得をＯ
倍からＺ倍に変化させることを特徴とするＡＧＣ
回路。[Claims for Utility Model Registration] A gain control circuit to which a television signal is supplied to a first input terminal; a detection circuit that generates a control signal from an output signal of the gain control circuit and supplies it to the gain control circuit; a delay circuit that delays the output signal of the gain control circuit by one horizontal scanning period and supplies the signal to a second input terminal of the gain control circuit, and the gain control circuit is configured to: The gain for the signal entering the first input terminal is
The gain for the signal entering the second input terminal is changed from 0 times to Y times (X<Y).
AGC characterized by changing from double to Z times
circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987189089U JPH0193884U (en) | 1987-12-12 | 1987-12-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987189089U JPH0193884U (en) | 1987-12-12 | 1987-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0193884U true JPH0193884U (en) | 1989-06-20 |
Family
ID=31480144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987189089U Pending JPH0193884U (en) | 1987-12-12 | 1987-12-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0193884U (en) |
-
1987
- 1987-12-12 JP JP1987189089U patent/JPH0193884U/ja active Pending
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