JPH0196785U - - Google Patents

Info

Publication number
JPH0196785U
JPH0196785U JP19254087U JP19254087U JPH0196785U JP H0196785 U JPH0196785 U JP H0196785U JP 19254087 U JP19254087 U JP 19254087U JP 19254087 U JP19254087 U JP 19254087U JP H0196785 U JPH0196785 U JP H0196785U
Authority
JP
Japan
Prior art keywords
inverter
switching elements
induction motor
shielded wire
shield
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19254087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19254087U priority Critical patent/JPH0196785U/ja
Publication of JPH0196785U publication Critical patent/JPH0196785U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のインバータの要部を示す電気
回路図、第2図は従来のインバータの接続を示す
ブロツク構成図、第3図は従来のインバータでト
ランジスタをスイツチング素子として用いた場合
の電気回路図、第4図はインバータにFETを用
いた場合のゲートにのつてくるスパイクノイズを
示す概念図である。 1〜6……FET、11,12……ゲート信号
線(シールド線)、101……商用電源、104
……アンプ基板(制御基板)、105……誘導電
動機(IM)、110……インバータ。
Fig. 1 is an electric circuit diagram showing the main parts of the inverter of the present invention, Fig. 2 is a block configuration diagram showing the connections of a conventional inverter, and Fig. 3 is an electrical diagram of a conventional inverter using transistors as switching elements. The circuit diagram, FIG. 4, is a conceptual diagram showing spike noise coming to the gate when FETs are used in the inverter. 1 to 6...FET, 11, 12... Gate signal line (shielded wire), 101... Commercial power supply, 104
...Amplifier board (control board), 105...Induction motor (IM), 110...Inverter.

Claims (1)

【実用新案登録請求の範囲】 商用電源を所望の周波数に変換し誘導電動機等
の負荷に電力を供給するようにし、FETをスイ
ツチング素子として用いたインバータにおいて、 FETのゲートと周波数制御用回路を搭載した
プリント基板との間に配線にシールド線を用いシ
ールドをアースに接続したことを特徴とするイン
バータ。
[Claim for Utility Model Registration] An inverter that converts commercial power to a desired frequency and supplies power to a load such as an induction motor, and uses FETs as switching elements, which is equipped with an FET gate and a frequency control circuit. An inverter characterized in that a shielded wire is used for wiring between the printed circuit board and the shield is connected to ground.
JP19254087U 1987-12-18 1987-12-18 Pending JPH0196785U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19254087U JPH0196785U (en) 1987-12-18 1987-12-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19254087U JPH0196785U (en) 1987-12-18 1987-12-18

Publications (1)

Publication Number Publication Date
JPH0196785U true JPH0196785U (en) 1989-06-27

Family

ID=31483393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19254087U Pending JPH0196785U (en) 1987-12-18 1987-12-18

Country Status (1)

Country Link
JP (1) JPH0196785U (en)

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