JPH0197272U - - Google Patents

Description

[Brief explanation of the drawing]

1 to 5 show an embodiment of the integrated circuit according to the invention, in which FIG. 1 is a block diagram of the analog circuit portion, FIG. 2 is a circuit diagram of the determination circuit in the analog circuit, and FIG. The figure is a timing chart showing the digital output etc. from the judgment circuit in the test mode of the above analog circuit, Figure 4 is a block diagram of an analog/digital LSI having the analog circuit of Figure 1, and Figure 5 is the same as the above analog/digital LSI. FIG. 6 is a block diagram schematically showing the analog circuit portion in FIG. 1: Analog input terminal, 3: Analog output terminal, 5: Proportional calculator (analog calculator), 6: Integral calculator, 7: Judgment circuit, 8: Digital output terminal, 9: Deviation calculator, 21: Comparator , 10: Analog/digital LSI, 20: Digital circuit,
30: Analog circuit.

Claims (1)

[Claims for Utility Model Registration] In an integrated circuit having an analog circuit including an analog arithmetic unit, in a test mode of the analog circuit, a deviation between an analog input and an analog output subjected to arithmetic processing of the analog arithmetic unit is calculated. a deviation calculator that outputs the absolute value of this deviation; an integral calculator that integrates the absolute value of the deviation output from the deviation calculator; and a comparison between the output of the integral calculator and a reference potential for determination. An integrated circuit comprising: a comparator that provides a digital output corresponding to the quality of the characteristics of an analog arithmetic unit.