JPH0197635U - - Google Patents
Info
- Publication number
- JPH0197635U JPH0197635U JP19366287U JP19366287U JPH0197635U JP H0197635 U JPH0197635 U JP H0197635U JP 19366287 U JP19366287 U JP 19366287U JP 19366287 U JP19366287 U JP 19366287U JP H0197635 U JPH0197635 U JP H0197635U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- sample clock
- ready signal
- external sample
- control means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 claims 1
- 230000002265 prevention Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図の動作を説明するためのタイミン
グチヤートである。
１……外部サンプルクロツク整形回路、２，３
……アンドゲート、４……クロツク発生器、５…
…Ａ／Ｄ変換器、６，８……インバータ、７……
Ｄ形フリツプフロツプ、９……表示装置。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of FIG. 1. 1...External sample clock shaping circuit, 2, 3
...And gate, 4...Clock generator, 5...
...A/D converter, 6, 8...Inverter, 7...
D-type flip-flop, 9...Display device.
Claims (1)
レデイ信号を出力するＡ／Ｄ変換器と、 このレデイ信号に従つて前記外部サンプルクロ
ツクを前記Ａ／Ｄ変換器に加えるサンプルクロツ
ク制御手段と、 前記外部サンプルクロツクとレデイ信号の反転
信号に従つて前記Ａ／Ｄ変換器から出力されるデ
ジタル信号のメモリへの書込みを制御するメモリ
制御手段、 とで構成されたことを特徴とするＡ／Ｄ変換器
誤動作防止装置。[Claims for Utility Model Registration] An A/D converter that outputs a ready signal indicating a state in which an external sample clock can be accepted, and applying the external sample clock to the A/D converter in accordance with the ready signal. sample clock control means; and memory control means for controlling writing of the digital signal output from the A/D converter into the memory according to the external sample clock and an inverted signal of the ready signal. An A/D converter malfunction prevention device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19366287U JPH0197635U (en) | 1987-12-21 | 1987-12-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19366287U JPH0197635U (en) | 1987-12-21 | 1987-12-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0197635U true JPH0197635U (en) | 1989-06-29 |
Family
ID=31484443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19366287U Pending JPH0197635U (en) | 1987-12-21 | 1987-12-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0197635U (en) |
-
1987
- 1987-12-21 JP JP19366287U patent/JPH0197635U/ja active Pending
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