JPH0199183A - Image processor - Google Patents

Abstract

PURPOSE:To calculate the areas of images at respective areas at high speed by counting the number of picture elements expressing a specific feature image at every processing area on each horizontal scanning line based on image signals read out from an image pickup device and by referring to area signals, and adding the countings at every processing area. CONSTITUTION:Corresponding to plural processing areas set in the scope of a TV camera, windows W1-W3 are provided, and window signals are generates synchronizingly with the reads of image signals from the camera. The sequence pattern of the processing areas appearing in window signals along respective horizontal scanning lines is set preliminarily, and at the same time, data to designate the sequence pattern for windows W1-W3 appearing on each horizontal scanning line is set at every horizontal scanning line. In respective horizontal scanning lines, the number of image elements in terms of the logic AND signals of window signals and image signals is counted at every window on the respective horizontal scanning lines. In the meantime, the sequence pattern corresponding to every horizontal scanning line is read out, and the countings are added in accumulation in the unit of section of processing. As a result, image area data in each processing area can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] Windows are set corresponding to a plurality of processing areas set within the field of view of a TV left camera, and these windows are stored in advance in a memory. A window signal representing a window is generated in synchronization with reading out an image signal from the camera. In addition to setting in advance the order of processing areas that appear in the window signal for each horizontal scanning line,
For each horizontal scanning line, data specifying the order pattern of windows appearing on that horizontal scanning line is set.

In each horizontal scanning line, the number of pixels in the AND logic signal of the window signal and the image signal is counted for each window on each horizontal scanning line. On the other hand, image area data for each processing area is obtained by reading out the corresponding order pattern for each horizontal scanning line and cumulatively adding the above-mentioned count values for each processing area in accordance with the order in which the windows appear.

This processing is completed in one field scanning period, and can be performed on a very large number (for example, several hundred) of windows at once. Also, if you set up many windows arranged regularly like a mesh window,
Since the number of types of order patterns described above is reduced, data related to the window order can be compressed, and the memory area for storing this data can be reduced.

BACKGROUND OF THE INVENTION The present invention relates to an image processing device that processes an image signal (video signal) of an object obtained from an imaging device (TV left camera or video camera) to calculate the area of the object on the image.

A fundamental challenge in visual inspection devices using imaging devices, visual sensors that serve as the eyes of robots, and the like is how to extract the feature amounts of an imaged object. The feature amounts include the contour, area, center of gravity, and the like of the object. When multiple objects (or multiple parts of one object) exist within the field of view of the imaging device, it is necessary to obtain feature amounts for each of these objects (parts).

When calculating the area of an image of an object in a plurality of areas set within the field of view of an imaging device, conventionally there are a serial processing method and a parallel processing method. In the serial processing method, area calculation is performed for one area for each image of one screen, and this is repeated multiple times.

Therefore, it takes a long time to finish processing all the areas, which is a problem when considering real-time image processing. In the parallel processing method, as many circuits as there are regions are prepared to perform area calculation processing in each region, and processing in a plurality of regions is performed at once. Although real-time processing is possible according to this method, the amount of hardware (the circuit described above) is enormous, and there are problems with practicality in terms of space and cost.

In both the serial processing method and the parallel processing method described above, it is considered possible to put them into practical use if the number of regions is about a few, although they have the above-mentioned drawbacks.

However, if the number of areas exceeds that number, for example several tens, or more than the image side, there is no possibility of practical use.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus that has a relatively simple configuration and can quickly calculate the area of an image in each area regardless of the number of areas to be processed.

The image processing device according to the present invention includes a first storage means that stores in advance a plurality of processing regions set within the field of view of the imaging device, and a processing region stored in the first storage means that is scanned by the imaging device. means for synchronously reading out and generating an area signal representing a processing area; a second memory storing in advance a pattern of the order in which the plurality of processing areas set in the first storage means appear for each horizontal scanning line; means,
a third storage means for storing, for each horizontal scanning line, data specifying the order pattern of processing areas appearing in that horizontal scanning line; a fourth storage means, means for counting the number of pixels representing a predetermined characteristic image for each processing area on each horizontal scanning line by referring to the area signal based on the image signal read from the imaging device; For each line, the third storage means is referred to, and the order pattern of processing areas appearing in that horizontal scanning line in the second storage means is specified, and for each processing area appearing in that horizontal scanning line, the above specified According to the order in the ordered pattern,
means for updating the cumulative area value stored in the fourth storage means by adding the counted value by the counting means to the cumulative area value of the corresponding processing area stored in the fourth storage means; It is characterized by the presence of

The area calculation processing in the plurality of processing regions described above is performed within the maximum l field scanning period (generally 1 /
Go see -16,7m5) to complete. Therefore, according to this invention, extremely rapid processing is possible;
It is extremely effective for automatic visual inspections in factory automation that require real-time processing. Also, if order pattern designation data is provided for each horizontal scanning line.

A common ordering pattern can be used for multiple horizontal scan lines. General (; Even if the number of processing areas becomes enormous, the number of types of order patterns mentioned above generally does not increase that much, so the hardware configuration, especially the memory capacity, does not increase dramatically.

That is, the overall circuit configuration is not significantly affected, and the configuration can be kept relatively simple. This invention is particularly suitable for mesh-like processing or when processing areas are regularly arranged like a group of processing areas. In this way, it is possible to set a very large number of processing areas (for example, several hundreds is sufficient), and - because it is possible to set a very large number of processing areas on the screen, it is possible to increase the accuracy of image processing. This also makes it possible to recognize complex shapes.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows a field of view of an imaging device and a window (processing area) set therein. In this embodiment, the screen of the imaging device is composed of 256 pixels horizontally (x1 to x25B) and 242 pixels vertically (y-y).The 256 pixels arranged horizontally form a horizontal scanning line. Configure.

An arbitrary number of windows of arbitrary shapes are set at arbitrary positions on such a screen. In FIG. 1, three windows W1 to W3 are set for convenience of explanation, and all of these windows are rectangular. There are very few requirements on windows. For example, the size of the window must be 2×2 pixels or more, and the horizontal interval between the windows must be 1 or 2 pixels or more (in the vertical direction, the windows may be adjacent as long as they do not overlap). The window interval in the horizontal direction is determined in relation to the operating speed of a high-speed memory, etc., which will be described later. Therefore, it is possible to set up to 10,000 or more windows on one screen. The shape of the window is not limited to a rectangle and can be set arbitrarily.

Each window contains an image (binarized for convenience of drawing) as shown by hatching. This invention calculates the area (number of hatched pixels) of these images.
is calculated for each window. Regarding window Wl, this window W is X%X
9. It is set between Y2 and y. horizontal scanning line y2
The area (number of pixels) of the image on the top is N1□-3, N-3 on y3, N-4 on )/4, and N-4 on Y3.
It is N-2 on the top, and N-2 on y6. Therefore, the area of the image within the window W1 is ΣN11-3+3+4+2+2-14. The area of the image inside the other windows W 1 , W 2 , etc. is determined in the same way.

The procedure of the area calculation process according to the present invention explained using the above example can be summarized briefly as follows.

(1) For each horizontal scanning line, calculate the area (number of pixels) of the image in the window on this horizontal scanning line.

Measure each window individually.

(2) The individual measurement areas of each window obtained above are cumulatively added for each window.

Each window is numbered to distinguish between multiple windows. This is the Wl mentioned above.

It is represented by W , W , . . . , W (n is equal to the number of windows 2 3 n). As is well known, image signals are read out from an imaging device along horizontal scanning lines, and the horizontal scanning lines to be read out sequentially move in the vertical direction. There are multiple windows on the top horizontal scan line. For example, in FIG. 1, windows W1 and W3 are on scanning line y2.

Wl, W2, and W3 are applied on y, respectively.

In step (1) above, the area is measured for each window, so windows on one horizontal scanning line must be distinguished from each other. To that end, we have shown Figure 2 (
A vertical address (or horizontal line) table as shown in A) and a window table as shown in FIG. 2(B) are provided.

There are multiple scan lines with the same order of windows appearing when each horizontal scan line is scanned. On scan line y, windows appear in the order W 1 and W 2 , but on both scan lines y 2 and y4, windows appear in the order W, W, W3. Also, the appearance order of windows on scan lines y and y6 is W.

It is W2. The window table shown in FIG. 2(B) stores the order pattern in which windows appear in the same order for a plurality of horizontal scanning lines.

In this window table, the starting address WT
The two memory locations starting from 1 contain data (sequence pattern) indicating the order of windows appearing along scan line y2.
is stored in advance. Specifically, the data of this sequential pattern is composed of area value area Φ addresses (WA, WA3, etc.) of each window, as will be described later. The three memory locations starting from the top address WT2 store an order pattern that appears in common on scan lines y and y4, and this order pattern is composed of data (address data WA1°) representing windows arranged in the order of the windows that appear. WA, WA3). Similarly, a common order pattern for scanning lines y and y6 is stored in two storage locations starting from the top address WT3. In the window table, a plurality of storage locations (groups of storage locations or storage areas) that store at least one sequential pattern are given consecutive addresses.

The vertical address table has as many locations as there are horizontal scan lines, and these locations are sequentially addressed. In this embodiment, in order to simplify the explanation, the 1st to 242nd horizontal scanning lines correspond to the 1st to 242nd horizontal scanning lines.
A street address has been assigned. For each memory location, in order to specify the order pattern of windows that appear on the corresponding horizontal scanning line, the order pattern is stored at the start address of the memory locations (storage area) of the window table in which the order pattern is stored, or in relation to it. Address data is preset.

Three embodiments will be described later, but in the first embodiment, the address data stored in this vertical address table is one value less than the above-mentioned top address (for example, WT -1, WT2-1, etc.). (Figure 2 (
In (a) of A), the second and third embodiments, the start address (WTl.

WT2, etc.) ((b) in FIG. 2(A)).

In these embodiments, the address of the vertical address square is specified by the count value of a vertical counter that counts horizontal synchronization signals. Therefore, for example, in scanning the third scanning line y3, the count value of this vertical counter is 3, and the address data W is read from the vertical address table.
T2-1 (first embodiment) or WT2 (second and third embodiments) is read and the window is set by this address.
Since the start address of the table is specified, this scanning line y
W, W, W3 (area value area address WA
, WA, WA3).

If a window table stores data representing the windows that appear along a horizontal scanline in that order for every horizontal scanline, a very large number of windows (e.g., 10,000 children) If set, the amount of memory for the window table must be increased. This is because the same order pattern regarding the window appearance order will be registered multiple times. In this invention, when there is a common order pattern for multiple scanning lines, these are not stored redundantly, but one stored order pattern is specified by data in a vertical address table set for each scanning line. This allows the memory capacity to be reduced. This is especially advantageous if the windows are arranged regularly so that the ordering patterns often overlap.

In order to execute the process of step (2) above, which cumulatively adds the individually measured area of each window for each window,
As shown in FIG. 2(C), an area value area having a place for storing cumulative area values is provided for each window. In this area, the first memory location corresponds to the first window W1, and the address W A
t is attached. Similarly, the second and third memory locations are 2nd. This is to store the cumulative area value of the third window W, W3, and the address WA, WA3
is attached.

Returning to FIG. 2(B), the window table described above contains data representing each window as the address (WA, W) for that window in the area value area.
A2, etc.) are stored in the order of appearance according to the scan for each order pattern. Further, it is preferable to store data indicating whether the image whose two areas are calculated for each window is a white level image or a black level image at a binary level in this window table. In other words, the image signal from the imaging device is converted to black and white as described later, and the number of pixels at the white level or the number of pixels at the black level is measured as the area of the image. This data represents whether pixels are to be counted. This data is used to control a black and white inversion circuit which will be described later.

Prior to explaining the specific configuration of the image processing device, it is thought to be useful to provide an overview of the entire processing for one field image.

FIG. 3 shows the vertical synchronizing signal VD, measurement period signal, horizontal synchronizing signal HD, and window signal WD output during one field period.

The window signal WD is output from a window memory, which will be described later, in synchronization with scanning in the imaging device, and represents the set position of the window in each horizontal scanning line.

During the first horizontal scanning period (scanning line yt), the area of the image in each window on this first horizontal scanning line is measured. In this embodiment, as shown in FIG. 1, there is no window on the first horizontal scanning line. That is, the vertical counter counts the horizontal synchronizing signal HD, and the value of this counter becomes 1.

Since no data is stored in the storage location of the vertical address table addressed by this value 1, it is determined that no window exists and the above measurement is not performed.

In the second horizontal scanning period (scanning line y2), the value of the vertical counter that counts the horizontal synchronization signal HD is 2. The vertical address table memory location addressed by this value 2 contains address data WTI-1 (or WT,
) is stored, the memory locations of the window table with this address data as the first address (
It can be seen that the data is stored in the order of addresses WA and WA3.

When the window signal first rises.

From the above order pattern, it can be seen that this is the window of address WA1 (that is, window W1), and from the black and white level φ data (not shown), it can be seen that, for example, pixels at the black level should be counted. Therefore, the pixels of the dark level where the window signal for the window W1 is H level are counted, and when this signal falls, the cumulative area value (
This count value is added to (0 at first) and stored.

Next, since the window signal rises again, it is determined from the above sequential pattern that it is window W3, and in the same way, pixels at black level are added while the window signal is at H level. When the window signal falls, this count value is added to the cumulative area value at the storage location of address WA3 in the area value area and stored.

In the third horizontal scanning period (scanning line y3), address data W T 2 1 or W T 2 is similarly read out from the vertical address table addressed by the value 3 of the vertical counter that counts the horizontal synchronizing signal HD. , the window whose start address is specified by this
It is found from the storage locations (storage areas) of the table that windows appear in the order pattern of W, W, W3 on the third horizontal scanning line.

Therefore, when the window signal first rises, it is recognized that this window is the window Wi, and the pixels at the dark level where the window signal is at the H level are counted. When this window signal falls, this count value is added to the cumulative area value at the storage location of address WA1 in the area value area and stored.

Furthermore, when the window signal rises again and again in the same way, these windows are found to be windows W and W3, and the pixels at the black level during the period when the window signal is at the H level are counted. When the window signal falls, the count values are added to the cumulative area values of the storage locations at addresses WA and WA3 in the area value area and stored.

Similarly, the above process is repeated from the 4th horizontal scanning period to the 242nd horizontal scanning period, and the cumulative area value of each storage location in the 9 area value areas is added for each pixel count in the corresponding window on each horizontal scanning line. To go. And the second
When the 42 scanning periods are completed, the cumulative area value of each storage location in the 9 area value areas becomes a value representing the area of the image in each window.

The measurement period signal is kept at H level during the above-mentioned measurement and calculation, and after the measurement is completed on the last horizontal scanning line, it is inverted to L level until the next vertical synchronization signal. During the period in which the measurement period signal is at the L level, a given determination process regarding the object is performed using the area value in each window determined by the above process.

As described above, one field period (-18,7m5
), the image area within each of the many windows is measured, and judgments are made using these measured values, so extremely rapid real-time processing is possible.

FIG. 4 shows the image processing device of the first embodiment, and FIG. 5 shows its operation. In particular, the measurement of the windows W and W2 is performed on the third horizontal scanning line y3 in FIG. ■ Indicates the part to be performed. In FIG. 5, for convenience of drawing, the L level period between the window signals of windows W 1 and W2 is drawn a little longer.

Referring to these drawings, a camera 40 has a built-in image pickup tube or a solid-state electron carrier device (COD, etc.).

Outputs an image signal of the object. This image signal is sent to a synchronization separation circuit 41, which generates a clock pulse CK for each pixel in the image signal, and a horizontal synchronization signal HD.
and vertical synchronization signal VD are taken out. The image signal is then sent to the binarization circuit 42, where it is discriminated at an appropriate threshold level and converted into a binary code having white and black levels.

The binarized image signal is transferred to a black and white inversion circuit 43. The signal is input to the pixel counter 36 via the gate circuit 24. The black-and-white inversion circuit 43 is composed of an EX-OR (exclusive OR) circuit, and is controlled by the CPU10 based on the black-and-white level data of the window table described above. When the monochrome inversion signal applied to this EX-OR circuit is at L level, the input binary image signal passes through this circuit as it is, and when it is at H level, it is inverted and output. Gate circuit 24 is controlled by window signal WD and timing signal T1.

The window memory 20 is a kind of image memory,
It has a capacity that can store one screen's worth of binary data. This memory 20 has a window WI-W as shown in FIG.
n is set. For example, if the bit in the area within the window is 1. The window position is stored by writing bits outside the window to 0. The bit corresponding to each pixel in the window memory is addressed by an address signal input via multiplexer 25. The multiplexer 25 switches between the address signal applied from the CPU10 and the address signal applied from the address counter 26.

When setting a window in the window memory 20, an address is given by the CPU 10, and data to be written to the data input/output terminal of the memory 20 is given. On the other hand, in the measurement period mentioned above, the window
Memory 20 is in read mode and address counter 2
An address signal is given from 6.

The address counter 26 is cleared by the vertical synchronizing signal VD, counts the input clock pulses CK, and outputs an address signal represented by the counted value.

Further, when this count value reaches a value indicating that scanning has ended on the 242nd horizontal scanning line, a measurement end signal is output. This measurement end signal is sent to the CP via the I10 control circuit 13.
given to Ul0.

In addition to this measurement end signal, the CPU 1O is given a vertical synchronization signal VD, and based on these input signals,
PU10 creates a measurement period signal as shown in FIG. 3 and outputs it from the I10 control circuit 13.

When the window memory 20 is in the read mode, the window data stored therein is output based on the address signal generated from the address counter 26 as described above. The window data read from the memory 20 is converted into a serial signal by a P/S (parallel/serial) conversion circuit 21, and the window data is converted into a serial signal.
D and is sent to the gate circuit 22. Gate circuit 22
is controlled by the measurement period signal, and a window signal WD is output during the measurement period. This window signal WD is correctly synchronized with the image signal from the camera 40. In other words, one image signal is the m-th bit of the °C-th scanning line.
, the window signal also indicates the presence or absence of a window at the m-th bit of the scanning line.

The window signal WD is a signal that is at an H level at a bit position where a window is set, and at an L level at a location where a window is not set. This window signal WD is applied to the gate circuit 24 and timing control circuit 23.

The timing control circuit 23 receives the input window signal WD.
and the horizontal synchronization signal HD, the fifth signal based on the measurement period signal.
Various timing signals T, T as shown in the figure
, T, T, generates a read signal RD and a write signal WR. timing signal T. remains at H level for a certain short period of time from the falling edge of the horizontal synchronizing signal HD during the measurement period.

It controls a multiplexer 33 and a window counter 38, which will be described later. The timing signal T1 is a signal that remains at H level for a certain period of time (for example, about a scanning period of one or two pixels) from the falling edge of the window signal WD, and serves as an inhibit signal and a clear signal for the pixel counter 36. Timing signal T2 is window signal WD
This signal remains at H level for a period shorter than the above-mentioned fixed period from the time of falling of , and is used to control the multiplexer 33 and the latch circuit (latch 1) 31. The timing signal T3 is at H level for a short period from the falling edge of the timing signal T2, and this controls the multiplexer 33 and the latch circuit (latch 2) 32. The read signal RD is at the L level from the falling edge of the timing signal T3 to the falling edge of the timing signal T1, and remains at the H level during the other periods.
During the level period, the high-speed memory 30, which will be described later, is read.
mode. The write signal WR becomes H level during a predetermined period within the period when the read signal RD is L level,
When at H level, high speed memory 30 is set to write mode.

The gate circuit 24 is controlled by the window signal WD and an inverted signal of the timing signal T1.
The image signal passes through this gate circuit 24 only while D is at H level.

The high-speed memory 30 is, for example, a cache memory, and stores the above-mentioned vertical address table, window table, and area value area. The addresses of the vertical address table, window table, and area value area in this memory 30 are specified by an address signal inputted via a multiplexer 33. The multiplexer 33 receives the address signal YCT output from the vertical counter 34, the address signal applied from the CPU10, the address signal WCT input from the window counter 38 via the data bus, and the data bus from the latch circuit 31. The address signal given via the above timing signals T, T, T3 and the CPU1
One of these address signals is output based on a control signal (path shown) given from 0.

Writing address data (WT, -1, WT2-1, etc.) to the vertical address table at the start of measurement,
Address data to window table (WA
, WA3, etc.), clearing the cumulative area value of the area value area 1, and reading the area value from the area value area at the end of measurement are performed by CPU10.
At this time, the high-speed memory 30
Addressing is performed by CPU10.

The vertical counter 34 is cleared at the beginning of the measurement period by the vertical synchronization signal VD, and is then cleared by the input horizontal synchronization signal HD.
It counts the falling edges of YCT and outputs an address signal YCT (this is the address of the vertical address table) represented by the counted value.

timing signal T. Vertical counter 3 when is at H level
The output address signal YCT of No. 4 is applied to the high speed memory 30 via the multiplexer 33. At this time, the read signal R
Since D is at H level and the memory 30 is in read mode, the address data (WT
-1, WT2-1, etc.) is read and applied to window counter 38. and timing signal T. The address data read from the vertical address table in memory 30 at the falling edge of
The counter 38 is preset. This counter 38 counts the falling edge of the window signal WD inputted thereafter while adding it to this preset value.

When the timing signal T2 is at H level, the window
The output address signal WCT (which is the count value of the counter 38)
This address (of the window table) is applied to the memory 3o via the multiplexer 33. When the timing signal T3 is at H level, the address latched in the latch circuit 31 (addresses WA, WA3, etc. read from the window contention table, which are the addresses of the area value area) is applied to the memory 3o via the multiplexer 33. It will be done.

The adder 35 adds the count value of the pixel counter 36 and the cumulative area value of the area value area sequentially outputted from the memory 3°, and the addition result is given to the latch circuit 32, where it is latched. Afterwards, it is returned to the area value area of the memory 30. The latch circuit 31 (j) latches the addresses WA, WA3, etc. read from the window table of the memory 30 and supplies them as address signals to the memory 30 via the multiplexer 33 as described above.

CPUl0 is FROMI which stores the execution program.
I, and R A M which stores data such as measured area values and data generated during processing.
12 and the above-mentioned I10 control circuit 13.

As described above, the CPU 10 writes window data to the window memory 20, creates a vertical address table in the high-speed memory 30, creates a window conflict table, clears the area value area, and finally measures the area value. , and performs object determination processing based on the area value of each window.

In preparation for starting the measurement, window data is written to the window memory 20, and the vertical address table 5I' and window table creation 1 area value area in the high speed memory 30 are cleared.

Then, when the measurement period signal rises, the area of the image for each window is counted and cumulative addition processing is performed. This process will be explained with respect to the window W1 of the third horizontal scanning line shown in FIG. 5 as follows.

Before the third horizontal scan starts, the vertical counter 34
The count value is 2. Further, the cumulative area value of the address WA in the area value area is ΣN11''=N11.The content of the vertical counter 34 is a value WT1+1 that specifies the last window wA3 in the second horizontal scan.

In the first embodiment, the vertical address table shown in FIG. 2(A) (a) is used.

When the horizontal synchronizing signal HD falls, it is counted by the vertical counter 34, and the value of this counter 34 becomes 3. As the timing signal To rises, this value 3 is given to the high-speed memory 3o via the multiplexer 33, and address 3 of the internal vertical address table is specified and the address data WT2-1 stored in that storage location. is read out and preset in the window counter 38 at the falling edge of the signal To. The value of the window counter 38 becomes WT2-1.

Thereafter, when the window signal WD rises, the count value of the window counter 38 is incremented to become WT2. While the window signal WD is at H level, the number of black level pixels of the binarized image signal is counted by the pixel counter 36.
(The counter 36 receives the previous timing signal T1
(already cleared at the falling edge of ).

When the window signal WD falls, the pixel counter 36 stops counting. Since the timing signal T2 becomes H level, the count value WT2 of the window counter 38 is given as an address signal to the memory 30 via the multiplexer 33, and at this time, the read signal RD is at the H level and the read mode is set. The contents WA of the address WT2 of the window table are read and the timing signal T
It is latched by the latch circuit 31 at the falling edge of 2.

Subsequently, the timing signal T3 rises, so the latch circuit 31
The address W A t latched in is given to the memory 30 via the multiplexer 33, and since the mode is read, the contents of the address WA in the area value area Σ
N11'=N11 is read out and given to the adder 35. The adder 35 adds the counted value N1° of the pixel counter 3B and this ΣN11, and the result is latched into the latch circuit 32 at the timing of the fall of the signal T3.

Next, the read signal RD becomes L level, the write signal WR becomes H level, and the memory 30 enters the write mode. The output address WA1 of the latch circuit 31 is still applied to the memory 30 via the multiplexer 33 as an address signal. therefore.

Addition result latched in latch circuit 32 ΣN11+N1
2 is written to the storage location of address W A 1 in the area value area, thereby performing cumulative addition of area values for window W1.

Finally, at the falling edge of the timing signal T1, the pixel counter 36
is cleared in preparation for counting pixels in the secondary window.

FIGS. 6 and 7 show a second embodiment. In these figures, the same components as those shown in FIGS. 4 and 5 are denoted by the same reference numerals, and the explanation thereof will be omitted, and only the different points will be mentioned.

The timing control circuit 23 receives the input window signal WD.
, timing signals T, T, which are different from those of the above-mentioned first embodiment, based on the measurement period signal and the horizontal synchronization signal HD.
, T, outputs a read signal RD and a write signal WR. timing signal T. is the same as in the first embodiment. The timing signal T1 rises at the rise of the window signal WD and remains at H level for a short period of time. timing signal T
2 rises when the signal T1 falls, and falls a little after the fall of the window signal WD. The read signal RD falls at the fall of the timing signal T2 and remains at the L level for a short period of time, during which the write signal WR becomes the H level.

Gate circuit 24 is controlled only by window signal WD.

The pixel counter 36 is cleared at the fall of the write signal WR.

The latch circuits 31 and 32 are provided with timing signals T and T, respectively.
Controlled by the falling edge of 2. MULTI ■ Tibrexer 33 receives the above timing signal T. in addition to these timing signals T 1 and T 2 .

In the second embodiment (the same applies to the third embodiment shown later), the second
A vertical address table shown in Figure (A) (b) is used. Therefore, the timing signal T in the third horizontal scanning period. Address number data W T 2 is preset in the window Φ counter 38 at the falling timing of .

When the window signal first rises on the third scanning line, the timing signal T1 rises.

Since the address signal representing W T 2 of the window counter 38 is applied to the high speed memory 30, the address data WA is read from the window table and latched into the latch circuit 31 at the timing of the fall of the signal T1.

Next, since the timing signal T2 becomes H level, the address data WA1 latched in the latch circuit 31 is applied to the memory 30 via the multiplexer 33, and thereby the data ΣN11 of the 9 area value area is read out and the adder given to 35. While the window signal WD is at H level, the two-pixel counter 36 counts the black level pixels of the binary image signal. Therefore, in the adder 35, the count value of the pixel counter 36 which is being updated and the data ΣN
11 is added, and the added value is updated.

When the window signal WD falls, the count value of the pixel counter 36 becomes a constant value, so the addition result of the adder 35 also becomes a constant value Σ
N1 and N12, which are latched by the latch circuit 32 at the falling edge of the timing signal T2.

Next, when the write signal WR becomes H level and the memory 30 enters the write mode, the addition result latched in the latch circuit 32 is stored at address W A + in the area value area. The window counter 3SJ is now incremented at the falling edge of the window signal WD (the counted value becomes W2+1), but since the multiplexer 33 has selected the latch circuit 31, in the above storage process of the addition result, The area value area is addressed by the output address W A t of the latch circuit 31 . After this.

The pixel counter 3G is cleared by the fall of the write signal WR.

In this embodiment, since the cumulative addition value is simply written (stored) after the fall of the window signal, the period until the rise of the secondary window signal can be shortened. This means that the horizontal spacing between the windows can be narrower (for example, one pixel apart).

FIG. 8 and FIG. 9 show a third embodiment,
The configuration is more simplified. FIG. 9 shows such an operation on the second horizontal scanning line, and the count value Y of the vertical counter 34 is
Illustration of CT and horizontal synchronization signal HD is omitted.

The last count W1+2 of window counter 38 is meaningless.

The difference from the second embodiment shown in FIG. 6 is that the adder 35 and latch circuit 32 are omitted.

Here, the timing signal T. The timing signal T1 is generated by the read signal RD which rises after the falling edge of or the processing of the previous window, and the address data WA, Cj-1 to Cj for the next window is generated before the window signal of the primary window rises. n) from the window table. Then, the cumulative integration value ΣNjI is read out from the area value area using the address data WA by the timing signal T2 which rises in response to the fall of the timing signal T1, and is preset in the pixel counter 36 at the time of the fall of the signal T2. There is. Therefore, when the window signal WD rises to the primary level and the binarized pixel signal is applied to the pixel counter 3B, the pixel counter 36 counts the input signal additively from the preset value. The count value of the pixel counter 3B at the time when the window signal falls represents a new cumulative addition value, which is then stored in the corresponding storage area of the area value area.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the relationship between the screen of the imaging device and the windows set there. FIGS. 2(A), 2(B), and 2(C) are diagrams showing a vertical address table, a window table, and an area value area provided in the memory, and in FIG. 2(A), (a) shows the first embodiment. , (b) is the second. 7 shows a vertical address table of a third embodiment. FIG. 3 is a time chart for explaining the outline of the operation during one field period. FIG. 4 is a block diagram showing the first embodiment of the present invention, and FIG.
The figure is a time chart showing the operation. FIG. 6 is a block diagram showing the second embodiment, and FIG. 7 is a time chart showing its operation. FIG. 8 is a block diagram showing the third embodiment, and FIG. 9 is a time chart showing its operation. 10... CPU. 20... Window memory. 21... P/S conversion. Circuit. 23... Timing control circuit. 30... High speed memory. 31, 32... Latch circuit. 34... Vertical counter. 35... Adder, 36... Pixel counter. 38...・Window counter. 40...Camera, 42...Binarization circuit. Patent applicant: Tateishi Electric Co., Ltd. Representative, Patent attorney: Kenji Ushiku (1 other person)

Claims (1)

[Scope of Claims] A first storage means for storing in advance a plurality of processing areas set within the field of view of an imaging device; a means for generating an area signal representing the processing area, a second storage means for storing in advance a pattern of the order in which the plurality of processing areas set in the first storage means appear for each horizontal scanning line; a third storage means for storing, for each horizontal scanning line, data specifying the order pattern of processing areas appearing in that horizontal scanning line; a fourth storage means, means for counting the number of pixels representing a predetermined characteristic image for each processing area on each horizontal scanning line by referring to the area signal based on the image signal read from the imaging device; For each line, the third storage means is referred to, and the order pattern of processing areas appearing in that horizontal scanning line in the second storage means is specified, and for each processing area appearing in that horizontal scanning line, the above specified The cumulative area value stored in the fourth storage means is obtained by adding the count value by the counting means to the cumulative area value of the corresponding processing area stored in the fourth storage means in accordance with the order in the order pattern. An image processing device comprising means for updating.