JPH02103092A - Driving circuit and thin-film el display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive circuit and a display device using the circuit, and particularly to a drive circuit suitable for use in charging and discharging a capacitive load to a high voltage. The present invention relates to a circuit and a thin film EL display device using the drive circuit for driving data lines or scanning lines.

[Conventional technology]

Generally, driving capacitive loads such as EL panels and piezoelectric elements requires high voltage driving of several hundred volts, and the driving circuit thereof is required to have a high withstand voltage. Also.

A drive circuit for a capacitive load generally has a so-called push-pull configuration including a source-side switch for charging the load and a sink-side switch for discharging the load. Drive circuits for capacitive matrices such as EL panels are required to be made into monolithic ICs that integrate multiple channels, but since they must be driven at high voltages, integration is essential to reducing power consumption. This has become an important issue in this case.

As a prior art related to this type of drive circuit with low power consumption and improved current drive capability, for example, Japanese Patent Laid-Open No. 60
A technique described in JP-A-208119 and the like is known. This type of conventional technology uses a thyristor as a switch.

FIG. 4 is a circuit diagram showing an example of a drive circuit according to the prior art. In FIG. 4, 6 is a logic circuit, 7 is a buffer circuit, 8 is a thyristor, 9 is a diode, 10. '
11 is an NPNI-transistor, 13 is a capacitive load, 71
．． 72 is the PMO 51 to transistor.

In general, a capacitive load drive circuit includes a source-side switch for charging the load and a sink-side switch for discharging the previously charged load. In the prior art shown in FIG. 4, a thyristor 8 is provided as a source side switch, and an l'JPNh transistor 10 is provided as a sink side switch.

In FIG. 4, the anode of thyristor 8 is.

It is connected to a high voltage application terminal 1, its cathode is connected to an output terminal 4 to which a capacitive load 13 is connected, its anode gate is connected to the collector of an NPN transistor 11, and its cathode gate is connected to an NPNh transistor 11.
0 collector. Further, the anode of the diode 9 is connected to the cathode of the thyristor 8, and the cathode of the diode 9 is connected to the cathode gate of the thyristor 8. NPN) - The emitter of the transistor 11 is connected to the other high voltage application terminal 2 through the resistor 12.
and its base is connected to the PMO in the buffer circuit 7.
It is connected to the drain of S transistor 71. Further, the emitter of the NPN transistor 10 is connected to the other high voltage application terminal 2, and its base is connected to the drain of the PMOS transistor 72 in the buffer circuit 7. The source of each PMO3+-Langistaff 1.72 is connected to the low voltage power supply terminal 4. Further, a logic circuit 6 that controls the operation of the buffer circuit 7 according to a control input signal from the input terminal 5 is connected to the buffer circuit 7 . This logic circuit 6 can be constructed using a shift register, a latch circuit, etc. when the drive circuit is integrated with a large number of channels. capacitive load 13
has one end connected to output terminal 3 and the other end connected to terminal 14.
It is connected to the.

The operation of driving an EL panel using the drive circuit configured as described above will be described below.

In general, in an EL panel, a scanning side electrode to which a high voltage is sequentially and selectively applied, and a data side electrode to which a relatively low voltage is applied in synchronization with light-emission/non-light-emission data, intersect with each other. The EL layer is formed between both electrodes. The portion sandwiched between the scanning side electrode and the data side electrode functions as one pixel, and is equivalently a capacitive load. The emission starting voltage is, for example, JP-A-60
As described in Japanese Patent No.-97394, etc., the voltage is as high as about 200V. In addition, the EL panel is
Since it has a polarization effect, it is driven by alternating current driving. In other words, even if an EL pixel is first charged with a certain voltage polarity and then discharged after emitting light, polarization occurs in the direction that cancels out the voltage polarity that was previously applied inside the EL pixel, and the same polarity is generated again. When a voltage is applied to perform charge 2 emission, sufficient luminance cannot be obtained and the luminance tends to decrease. Therefore, in order to cause an EL pixel that has already emitted light to emit light again, it is necessary to apply a voltage with a polarity opposite to that of the previous time. As a prior art related to such an EL panel driving method, for example, Sharp Technique, 1987, No. 38
No. rTF-・EL display bidirectional Pu5h-P
A technique described in ``uQ Q Symmetrical Drive System'' is known.

The operation when the conventional drive circuit shown in FIG. 4 is applied to drive the data side electrode of the EL panel will be described next.

In this case, the first power supply terminal 1 in FIG.
Then, the second power supply terminal 2 is connected to GND (OV). As shown in the above literature, the power supply VD is EL
The voltage is set to about 50 .ANG., which is sufficiently lower than the light emission start voltage of the pixel. The capacitive load 13 corresponds to one pixel in the EL panel, and in reality, there are as many pixels as the number of scanning side electrodes for one data side electrode, but for simplicity, the fourth
In the figure, only 131 capacitive loads are representatively shown. Hereinafter, this capacitive load 13 will be referred to as a pixel 13. The terminal 14 to which one end of the pixel 13 is connected corresponds to one scanning side electrode if the output terminal 3 is one data side electrode.

Now, by applying a positive high voltage Vop to the scanning side electrode 14,
Consider the case where the pixel 13 emits light.

Note that the positive high voltage Vnp is ELii! If the 7ft pressure at which the light emission starts from the ii element 13 is 1Vrl, then V++p>I
Vt I te, and Vup −Vo< l VT l
D is set. Vo is.

This is the voltage of the power supply connected to the first power supply terminal 1.

In this state, if the PMOS transistor 72 in the buffer circuit 7 is controlled to be turned on and the PMOS transistor 71 is controlled to be turned off, the base current is supplied from the low voltage power supply terminal 4 to the NPN transistor 10 via the PMOS transistor 72, and the NPN transistor 10 is turned on. Turns on. It is assumed that a low voltage power supply of about 5 cm is connected to the low voltage power supply terminal 4.

When the NPN transistor 10 is turned on, the output terminal 3,
That is, the data side electrode has the GND potential, which is approximately the same potential as the power supply terminal 2. At this time, in the thyristor 8, since the PMO8+- transistor 2 and the NPN transistor 11 are off, no gate drive current flows, and the cathode gate of the thyristor 8 is biased to the GND potential by the NPN l- transistor 10. It's off because it's there.

In this state, since the positive high voltage V++p of the terminal 14, that is, the scanning side electrode is applied, the voltage across the pixel 13 is V
Since the voltage becomes np and exceeds the light emission start voltage vT, the pixel 13 emits light.

When the pixel 13 does not emit light, the PM in the buffer circuit 7
The OS transistors 71 and 72 are controlled to be turned on and off, respectively, thereby turning the NPN transistors 11 and 10 on and off, respectively.

When the NPN transistor 11 turns on, the thyristor 8
turns on when the gate current is extracted from its anode gate. As a result, the output terminal 3, that is, the data side electrode outputs the potential VD of the power supply applied to the terminal 1. In this state, even if a positive high voltage VHP is applied to the terminal 14, that is, the scanning side electrode, the voltage across the pixel 13 will be V
The pixel 13 does not emit light because it becomes op-Vo and does not reach the second light emission voltage VT.

After controlling the emission (or non-emission) by charging the pixel 13 with the positive high voltage VHP described above, it is necessary to bias the scanning side electrode to OV and discharge the pixel 13 in order to prepare for the next drive timing. There is. Due to the polarization effect of the pixel 13 described above, the next drive must be performed by inverting the polarity of the voltage applied to the pixel 13, and in this case, a negative high voltage V old is applied to the scanning side electrode. is applied to pixel 13
emits light. This negative high voltage VIIN is l Vll
N'l < VT, and I V)IN I + Vo
>Vt4. - set.

First, when making the pixel 13 emit light, contrary to the case using the positive high voltage VIIP described above, the thyristor 8 is turned on, and the voltage of the power supply connected to the terminal 1 from the output terminal 3, that is, the data side type, is turned on. Output Vo. In this state, a negative high voltage VHN is applied to the terminal 14, that is, the scanning side electrode 14.
When the pixel 13 is applied, the voltage applied to both ends of the pixel 13 becomes IVHN l +Vo, exceeding the light emission starting voltage ■r, and emits light.

On the other hand, when the pixel 13 does not emit light, the NPN transistor 10 side is turned on, and the output terminal 3, that is, the data side electrode is set to approximately the GND potential. In this state, if a negative high voltage VIIN is applied to the terminal 14, that is, the scanning side electrode,
The voltage applied to both ends of the pixel 13 is l VIIN
1, the light emission starting voltage VT is not reached, and no light is emitted.

As mentioned above, when the conventional drive circuit shown in FIG. 4 is applied to drive the data side electrode, this circuit is
According to the data sent to the logic circuit 6, the thyristor 8 or the NPN transistor 10 is turned on, and the voltage VD or 0 is sent to the output terminal 3, causing the pixel 13 to emit light.
Non-emission can be controlled.

Next, the operation when the drive circuit shown in FIG. 4 is applied to drive the scanning side electrode of the EL panel will be described.

In this case, the output terminal 3 in FIG. 4 corresponds to one scanning side electrode, and the terminal 14 corresponds to one data side electrode. As mentioned above, the scanning side electrode is driven by the positive high voltage Vnp.
This is performed by alternately applying a negative high voltage VHN and a negative high voltage VHN to the scanning side electrode. Therefore, in the drive circuit shown in FIG. 4, the second power supply terminal 2 is floated,
If necessary, it is biased to a negative high voltage VIIN or Ov, and the first power supply terminal 1 is biased to a positive high voltage Vup or some low voltage (for example 30v).

Note that the low voltage power supply terminal 4 for the logic circuit 6 and the buffer circuit 7 always connects the second power supply terminal 2 to L! As the i standard, a low voltage of about 5 .mu. is applied.

First, when outputting the positive high voltage Vup to the output terminal 3, that is, the scanning side electrode, the first '1π source terminal 1 is biased to the positive high voltage VII+', and the second power supply terminal 2 is biased to oV. , In this state, the thyristor 8 is turned on. The thyristor 8 is turned on in the same manner as when the drive circuit shown in FIG. 4 is used to drive the data side electrode. The scanning side electrode to which the positive high voltage ■old is applied is only one selected scanning electrode in the EL panel, and the driving circuit driving the other non-selected scanning electrodes is the NPN transistor 10. By turning on, the voltage applied to the non-selected scan electrodes is set to approximately 0.

The pixel 13 is prevented from emitting light.

Next, when outputting the negative high voltage VIIN to the output terminal 3, that is, the scanning side electrode, the first power supply terminal 1 is set to 30V, for example.
and the second power supply terminal 2 is biased to a negative high quasi-voltage VI
It is biased to IN, and NPN1 to transistor 10 are turned on in this state. As a result, the negative high voltage VHN from terminal 2 is applied to the selected scan electrode from NPNI to
Rancita 10. It is sent out via output terminal 3. on the other hand,
The drive circuit connected to the non-selected scan electrode is connected to the 30V applied to the power supply terminal 1 with the thyristor 8 turned on.
voltage is sent from the output terminal 3 to the scanning electrode, and the voltage of
prevents it from emitting light.

In the example of driving the pixel 13 described above, the first power supply terminal 1
30V to bias the first '? rf, source terminal 1 upper terminal 1P N l - through transistor 11 to second power supply terminal 2 to thyristor 8 goo 1 - the voltage condition through which the drive current flows, that is, the voltage of terminal 1 > the voltage of terminal 2 is satisfied. If so, it may be Ov.

[Problems to be Solved by the Invention] As described above, the drive circuit for the EL panel is required to have a withstand voltage of 50V to several hundred V. In the conventional circuit explained with reference to FIG. 4, the thyristor 8 and the NPN transistors 10 and 11 must be constituted by high voltage elements.
When this circuit is integrated into a large number of channels, the three high voltage elements are required for each channel. In general, high voltage elements require a large element size to ensure voltage resistance, and in circuit integration, it is desirable to reduce the number of high voltage elements as much as possible by reducing chip size.

The conventional technology shown in FIG. 4 uses the NPNI-transistor 11 only to turn on the thyristor 8, and is not directly involved in driving the load, which has the problem of poor utilization of high voltage elements. This has the problem of high power consumption.

As a technology related to a drive circuit with reduced power consumption, there is a technology described in Japanese Patent Application No. 15829/1983, which has already been proposed. This technique provides a one-shot circuit in the logic circuit 6, and connects a PMOS transistor 71 and N P N
By pulse-operating the h-range stabilizer 1, it is possible to effectively reduce the drive current of the thyristor 8, thereby reducing the power consumption. However, this technique has the problem that the inclusion of a one-shot circuit complicates the logic circuit 6 and increases the chip area.

The purpose of the present invention is to solve the problems of the prior art described above,
The object of the present invention is to provide a drive circuit that can reduce the number of high-voltage elements, reduce chip size during integration, and further reduce power consumption. An object of the present invention is to provide a thin film EL display device using the present invention.

[Means to solve the problem]

According to the present invention, the above object is to provide a low voltage switching element between the NPNI transistor 1o and the second power supply terminal 2 in the drive circuit according to the prior art shown in FIG. Logic circuit 6 through 7
This is achieved by controlling the on/off state in response to signals from the

[Effect]

When the voltage switching element is turned on and the PMO3I transistor 2 in the buffer circuit 7 is turned on, the base current of the N P N h transistor 0 flows from the emitter of the NPNI transistor 10 to the second voltage via the switching element. Flows to the power supply terminal 7-2, NPN l~
Turn on transistor 10.

On the other hand, 1) If the low voltage switching element 1 is turned off and PMO8+-Rangistaph 2 is turned on, the NPN
The base current of the transistor 10 flows to the collector side of the NPN transistor 10 and flows into the cathode gate 1- of the thyristor 8, so that the thyristor 8 can be turned on. In this case, since this current is supplied from the low-voltage power supply terminal 4, it is automatically extinguished when the thyristor 8 is turned on and the voltage at the output terminal 8 increases. Also,
There is no need to reduce the gate drive current of the thyristor 8 from the power supply terminal 1 to which a high voltage is applied, thereby reducing power consumption.

As described above, by providing the low voltage switching element, it becomes possible to turn on the thyristor 8 from the side of the NPN transistor 10, which is the sink side switch. For this reason, the present invention provides N P for driving the thyristor 8.
The transistor 11 can be eliminated, the number of high-voltage elements can be reduced, and power consumption can also be reduced as described above.

〔Example〕

Hereinafter, embodiments of the drive circuit and thin film EL display device according to the present invention will be described in detail from the IJ plane.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention. In FIG. 1, 15 is a low voltage switching element, and the other symbols are the same as 9j in FIG.

The first embodiment of the present invention shown in FIG. , a diode 9 whose anode is connected to the cathode of the thyristor 8, its collector connected to the cantilever gate 1 of the thyristor 8, and its emitter connected to the second source terminal 2 via the low voltage switching element 15, respectively. The base of the NPN transistor 10 is connected to the PMOS transistor in the buffer circuit 7.
Connected to the first line of transistor 72, PMO3+
- the source of the Langistav 2 is connected to the low voltage power supply terminal 4; The circuit shown in FIG. 1 also includes a logic circuit 6 for controlling the buffer circuit 7 and the output section in accordance with an input signal applied to the input terminal P5. ] The low voltage switching element 15 mentioned above can be controlled to be turned on or off in accordance with the output signal of the logic circuit 6.

The operation of the first embodiment of the present invention shown in FIG. 1 having the above-described structure will be described when it is used for driving the data side electrode of an EL panel.

In this case, the first power supply terminal 1 is connected to the power supply vn, and the second power supply terminal 2 is connected to GND, that is, Ov, as in the case of the prior art shown in FIG. 4 described above. Also,
Output terminal 3 corresponds to +11 on the 1 data side electrode, and terminal 14
corresponds to one scanning side electrode. Note that a low voltage power source of about 5 cm is connected to the low voltage power source terminal 4.

In the first embodiment shown in FIG. 1, a voltage VO or OV is output to the output terminal 3, that is, the data side electrode,
The fact that the pixel 13 can be controlled to emit light or not emit light is the same as in the prior art described above.
Only the operation will be explained as to whether o or 0■ is sent to the output terminal 3, that is, the data side electrode.

First, when the thyristor 8 is turned on and the voltage Vo applied to the first power supply terminal 1 is sent to the output terminal 3,
In the illustrated circuit, the low voltage switching element 15 is turned off and the PMO 3i in the buffer circuit 7 is turned off.

Landistav 2 is turned on. When the PMOS transistor 72 is turned on, the PMOS transistor 72 is connected from the low voltage power supply terminal 4 to the PMOS transistor 72
NPNl-transistor 10 via S transistor 72
However, since the low voltage switching element 15 is off, this base current is NPN
It does not flow to the emitter side of the transistor 10, but flows to the collector side, and flows into the cathode gate l~ of the thyristor 8.

As a result, the thyristor 8 is turned on, and the output terminal 3,
That is, the voltage Vo applied to the terminal 1 is sent to the data side electrode. Since the base current to the NPN transistor 10 is supplied from the low voltage power supply terminal 4, when the thyristor 8 is turned on and the potential of the output terminal 3 rises, and the voltage approaches the voltage of the low voltage power supply terminal 4, automatic It stops flowing. After that, when the potential of the output terminal 3 further increases, this voltage is held at the collector-base junction of the NPN l-transistor 10, so that the crystal type is not applied to the low-voltage switching element 15, the PMO3+-ransistor 2, etc. .

When the NPN transistor 10 is turned on and the OV applied to the second power supply terminal 2 is sent to the output terminal 3,
In the illustrated circuit, the low voltage switching element 15 is controlled to be turned on, and the PMOS transistor 72 in the buffer circuit 7 is controlled to be turned on. In this case, since the low-voltage switching element 15 is on, the NPN transistor 10 is supplied from the low-current power supply terminal 4 via the PMO3+-Rangistaft 2.
The base current flows to the emitter side, and the transistors 10 to NPNI perform transistor operation and are driven on. When the N I ) N )- transistor 10 is turned on, the GND potential OV connected to the second power supply terminal 2 is sent to the output terminal 3 via the low voltage switching element 15° NPN transistor 10, and is output. terminal 3,
That is, the potential of the data side electrode is lowered to approximately OV.

In the above-described first embodiment of the present invention made by Gino, when the thyristor 8 is turned on when the potential of the output terminal 3 is in a high potential state, the circuit of the embodiment
P N l” transistor 10 side is turned on, output terminal 3
After lowering the potential of the thyristor, the thyristor is controlled to be turned on.

Next, the operation when the first embodiment of the present invention shown in FIG. 1 is applied to drive the scanning side electrode of an EL panel will be described.

In this case as well, as in the case of the prior art shown in FIG. is biased to a positive high voltage V++p or a certain low voltage, and a low voltage of about 5■ is always applied to the low voltage power supply terminal 4, where i(!!) is based on the second power supply terminal 2.

The output terminal 3 corresponds to one scanning side electrode, and the terminal 14 corresponds to one data side electrode.

First, when sending a positive high voltage Vop to the output terminal 3,
In the circuit shown in FIG. 1, the first power supply terminal 1 is connected to a positive high voltage V
The thyristor 8 is turned on while being biased to HP and the second power supply terminal 2 being biased to 0■. The on-1 drive of the thyristor 8 is performed by turning the PMO3+-Rangistaff 2 in the buffer circuit 7 with the low voltage switching element 15 turned off, as in the case where the embodiment of the present invention described above is used to drive the data side electrode. When turned on, the base current applied from the low voltage power supply terminal 4 to the NPN transistor 10 via the PMOS transistor 72 is N P N I
- It is carried out by flowing into the collector side of the transistor 1o and flowing into the cathode gate 1 of the thyristor 8. Furthermore, when sending out 0■ to the output terminal 3, the circuit of FIG. 1 turns on the low voltage switching element 15 and
The transistor 10 is controlled to be turned on.

Next, when sending out the negative high voltage VIIN to the output terminal 3, the circuit shown in FIG.
NPNI-
Transistor 10 is turned on. At this time, the low voltage switching element 15.

It is in the on state. For this operation, the non-selective scan′
When turning on the thyristor 8 in the drive circuit connected to the IF 1, it is necessary to pay attention to the potential relationship between the output terminal 3, that is, the unselected scan electrode in this case, and the low voltage power supply terminal 4. That is, when the potential of the second power supply terminal 2 decreases, the potential of the low voltage power supply 316 terminal 4 also decreases, so that the NP
N l-transistor 10 and low voltage switching element 15
In the drive circuit of the channel in which the thyristor 8 is turned off, the potential of the low voltage power supply terminal 4 becomes lower than the potential of the output terminal 3, and there is a possibility that the thyristor 8 cannot be turned on. Such a phenomenon can be avoided by lowering the potential applied to the second power supply terminal 2 after the thyristor 8 is turned on.

As described above, the first embodiment of the present invention can be applied to drive either the data side electrode or the scanning side electrode of an EL panel. Further, according to the first embodiment of the present invention, the high voltage PNPI transistor 11 which is used in the conventional technology for turning on the thyristor 8 can be omitted, and the number of high voltage elements can be reduced. ,
Chip size during integration can be reduced. Furthermore, according to the first embodiment, the groove 1-1' of the thyristor 8
Since the dynamic current can be supplied from the low-voltage power supply side and the conduction period can be set to the minimum time required for the thyristor 8 to turn on, power consumption can be reduced.

FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the present invention. In FIG. 2, 15.74 is an NMO 51 to a transistor, 73 is a PMOS transistor, and other symbols are the same as in FIG. 1.

In a second embodiment of the present invention shown in FIG. 2, the low voltage switching element 15 is constructed of an NMO3I transistor. In this second example.

The drain of the NMOS transistor 15 is connected to the emitter of the NPN transistor 10, and its source is connected to the second
The gate is connected to the power supply terminal 2 of the PMO 51 whose source is connected to the low-voltage power supply terminal 4, and the train of Ranjistaph 3 whose source is connected to the second power supply terminal 2.
Connected to the 1-rain of MOS l-Landistav/l.

In the second embodiment configured in this way, the buffer circuit 7
By controlling PMO3+-Rangistaph 3 in
The I-transistor 15 is turned off, and in this state, P
By turning on the MOS transistor 72, PMO3+
- The base current applied to the NPN transistor 10 through the transistor 2 flows to the collector side, so that the thyristor 8 can be turned on. Further, in this second embodiment, the PMOS transistor 73 is turned on and the NMO3
+- By controlling Langistav 4 off, NM
O3I- transistor 15 is turned on, and in this state, if PMO5+- transistor 2 is turned on, NPN
The base current of the transistor 10 flows to the emitter side, and N
The PN transistor 10 can be turned on.

According to the second embodiment of the present invention described above, by providing the NMO8I-transistor 15 as the low-voltage switching element 15, the thyristor 8 and the NPNI-transistor can be connected without providing a high breakdown voltage element for turning on the thyristor 8. 10 can be controlled to be on, and the same effects as in the first embodiment of the present invention can be achieved.

Further, in the second embodiment of the present invention described above, the switching element 15 was configured with an NMOS transistor, but the switching element 15 may be a PMOS transistor, an NPMOS transistor, or an NMOS transistor.
N, PNPI-transistors, etc. can also be used.

FIG. 3 is a circuit diagram showing the configuration of a third embodiment of the present invention. In FIG. 3, 16 is a low voltage diode, 101,
102 is an NPN transistor, and other symbols are the same as in FIG.

A third embodiment of the invention, shown in FIG.
It is composed of Darlington-connected transistors. In this third embodiment, the emitter of the NPN transistor 101 is connected to the low voltage switching element 15.
The low voltage switching element 15 is connected to the base of the transistor 102 via NPNI, and the low voltage switching element 15 is constituted by an NPN transistor.

The first and second aspects of the present invention shown in FIGS. 1 and 2 described above
In the embodiment, since the low voltage switching element 15 is connected to the emitter of the NPNI transistor 1o, the current of the N P N h transistor 0 is limited by its on-resistance component. A third embodiment of the invention, shown in FIG. 3, avoids the current limitation described above.

In FIG. 3, if the PMOS l-rangestaff 3 is turned off, the low-voltage switching element by the NPN transistor is turned off, and the PMOS transistor 72 is turned on,
The base current flowing into the NPN transistor 101 is N
It escapes to the collector side of the PNI transistor 101, flows into the cathode gate 1 of the thyristor 8, and the thyristor 8 is turned on.

On the other hand, with PMOS1-Langistav 3 turned on, N P
When the low-voltage switching element 15 by the N I transistor 15 is turned on and the PMOS l transistor 2 is turned on, the base current flowing into the NPN transistor 101 flows to the emitter side and passes through the switching element 15 to the N P N I- It flows into the base of transistor 102. As a result, the NPNI transistors 101 and 102
operates as a Darlington NPN transistor and is driven on.

In addition, in FIG. 4, when the low voltage diode 16 provided between the cathode of the thyristor 8 and the output terminal 3 turns on the NPN transistor 10 side, its base potential,
That is, the base potential of the NPN I transistor 101 is lower than that in the first and second embodiments of the present invention described above.
This is inserted to prevent the current from being shunted to the cathode gate side of the thyristor 8 since the built-in voltage between the emitters becomes higher, and it may be a resistor or the like.

Furthermore, in the embodiment shown in FIG. 4, the collectors of the NPN transistors 101 and 102 are connected in common, so that when integrated, both can be formed in the same element region.

In the third embodiment of the present invention described above, the NP
hFE of the current flowing into the base of the N transistor 102
It is possible to obtain double the output current by using the Green-one connected transistor constituting the NPN transistor 10, and it is possible to improve the load driving ability compared to the first and second embodiments of the present invention. can. Note that hFE is NP
NI- is the current amplification factor of the transistor 102.

According to the third embodiment of the present invention described above, the first embodiment of the present invention
In addition, the same effects as in the second embodiment can be obtained, and the load driving ability can be improved.

〔Effect of the invention〕

As explained above, according to the present invention, the ON control of the source-side high-voltage switching element can be performed by the low-voltage switching element provided in the sink-side high-voltage switching element section, so that the number of high-voltage switching elements can be reduced and integrated. In addition, since the source-side high-voltage switching element can be turned on by supplying current from the low-voltage side, power consumption can be reduced. As a result, according to the present invention, it is possible to provide an integrated circuit for driving thin film EL with a small chip area, and it is possible to provide a small thin film EL display device with low power consumption.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 illustrate the first embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of the second and third embodiments, and FIG. 4 is a circuit diagram showing the configuration of an example of the prior art. 6...Logic circuit, 7...Buffer circuit, 8...Thyristor, 9,16...Diode, 10,11゜10
1.102...NPN transistor, 13...Capacitive load (pixel), 71,72.73...PMOS transistor. House map, Figure 3, Figure 2-B, High school map, 4

Claims (1)

[Claims] 1. A thyristor with a gate terminal that supplies current to a load;
A drive circuit comprising a transistor that draws current from a load, wherein a gate drive current of the thyristor is supplied via a base-collector junction of the transistor. 2. A thyristor with a gate terminal that supplies current to the load,
1. A drive circuit comprising a transistor that draws current from a load, the drive circuit comprising a switching element connected in series to an emitter of the transistor. 3. The transistor that draws current from the load is the first transistor.
and a second transistor connected in Darlington, and a switching element is provided between the emitter of the first transistor and the base of the second transistor. The drive circuit described. 4. The drive circuit according to claim 2 or 3, wherein the switching element is a MOS transistor. 5. The drive circuit according to claim 2 or 3, wherein the switching element is a transistor. 6. The thyristor that supplies current to the load has a pn junction element connected between its gate and cathode, and is provided between the first power supply terminal and the output terminal, and the transistor that draws current from the load is 6. The drive circuit according to claim 1, wherein the drive circuit is provided between the gate of the thyristor and the second power supply terminal. 7. The drive circuit according to claim 1, wherein the load is a capacitive load. 8. In a thin film EL display device comprising a scanning side electrode and a data side electrode arranged to intersect with each other and an EL layer provided between the two electrodes, driving of the scanning side electrode or the data side electrode is described in the above patent. Claims 1 to 6
A thin film EL drive circuit characterized in that it is performed using the drive circuit according to item 1 of the items.