JPH0210598A - Memory device - Google Patents

Abstract

PURPOSE: To program a flash memory device via a data port and to enable an erasing command port architecture by incorporating a circuit means into the same semiconductor chip as a memory executing erasing, programing and erasing/programming test in a circuit. CONSTITUTION: A data bus 20 is connected to an input/output buffer 21, and data to be inputted into a memory array 11 is connected from the bus 23a via a data latch 22. On the contrary, data to be outputted to the data bas 20 from the memory array 11 are connected to an I/O buffer 21 from a bus 23b via a sense circuit 101, thereafter data are outputted to the data 20. Input data are also connected to a command port controller 30 via the bus 23a. External signals WE and CE are further received with the command port controller 30, and control signals are fed to an address latch 13, the data latch 22, an eraser voltage generator 24, a program voltage generator 25 and an erasing/ programming test generator 26. External signals CE and DE are connected to a chip/output enable logic circuit 27.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to an electrically programmable erasable read-only memory (EEF) fabricated from metal oxide semiconductor (MOS).
The present invention relates to the field of ROM (ROM) and programmable read only memory (EPROM) with floating gates.

[Prior art and problems to be solved by the invention] The most commonly used gFROM cell is based on an insulator)
has a fully enclosed electrical floating gate;
This floating gate is usually arranged between a source region and a drain region formed in a silicon substrate. In early EFROM cells, U.S. Patent No. 3,660,
As in the device described in '819, charge was injected into the insulator by avalanche injection. Late EFR
OM is U.S. Pat. No. 4,142,926, No. 4,11
No. 4,255 and No. 4,412,310, channel injection was used to charge the floating gate. Erasing such an EPROM is accomplished by irradiating the array with ultraviolet light.

Erasable EPROMs (EEFROMs) are also commercially available in which charge is applied to and removed from the floating gate by passing the charge through a thin oxide region formed on the substrate (see US Pat. U.S. Pat. No. 4,203.158) and a configuration for removing electric charge through the electrode (see U.S. Pat. No. 4,099,
1913).

In such an EEPROM cell, the area of the substrate is not reduced as compared to an EFROM cell. Various methods have been implemented to reduce the size of memory arrays by increasing cell density. One of the methods is the U.S. patent 4
, No. 432,075. Also, U.S. Pat. No. 4,266,283 describes arranging EEPROMs in an array and selecting various functions to be performed in the memory array.

EFROM is most often removed from printed circuit boards for two purposes: erasing and programming.

Special programming equipment is used to program the cells. The device also verifies that the cells are properly erased and programmed. During programming, the conductivity of the cell decreases as electrons are transferred to the floating gate. The operation of this EPROM device is also well known.

EEPROMs differ from EPROMs in that EEPROMs are typically programmed and erased while attached to the same circuitry (eg, a printed circuit board) used to read data from memory. That is, no special programming equipment is used. In some cases, "on-chip" circuitry is used to verify that programming has been performed properly. US patent cylinder 4,
No. 460.982 discloses an intelligent EEPROM comprising means for performing both programming and erasing.
is listed.

More recently, erasable EP ROMI E
A new type of E=PROM has appeared, but this device is
Sometimes called Flash J EPROM or gKPROM. In this flash memory, the entire array is electrically erased at the same time. The cells themselves use only a single device per cell. Such cells are described in the aforementioned co-pending application, Application No. 892,446. Another configuration related to this is rEEE Jou
rnal of 5old-8tateC1rcui
ts, Vol, 5C-22, Na4 (198
A paper by Masuoka et al. published in April 2013 rA 2
56-Kbit F1a5h E PROM Usin
g Triple-PolysLllcon Tsc
Also seen in hnologyJ. The present invention is directed to the use of these cells.

Flash memory devices that erase electrically present other problems, particularly over-erasure. Because so much charge is removed in the remainder, the device becomes in a state similar to U depletion. After erasing, a test of the cell will be required to verify that the floating gate is erased but not very positively charged.

Utilizing in-circuit erasure in flash memory creates another problem. That is, it is necessary to add new signals/command lines to perform erasing and programming of the flash memory. Normally, an added line requires the addition of a corresponding bin on the memory chip, but this does not present a problem when designing a new circuit board, system, etc.

However, when using flash memory in place of existing gpRoM/gEPROM, bin compatibility is an essential condition. Because of the need for auxiliary control lines for erasing and programming, direct bin-to-bin compatibility is not possible unless some architectural change is made within the flash memory device to allow erasure and reprogramming. I can't.

[Means for solving problems]

The present invention provides a command boat architecture for programming and erasing flash memory devices via a data boat. Circuit means are integrated into the same semiconductor chip as the memory to perform erasure, programming and erase/program verification within the circuit. A command boat controller is coupled to accept instructions from a data line coupled to an associated processor. Instructions written to the command boat controller provide the instructions necessary to generate the control signals to perform erase and programming of the memory and to inspect the contents after the erase and program operations have been performed. do.

The command boat is comprised of a command boat controller, data registers coupled to the data bus for accepting programming data, and address registers coupled to the address bus for accepting address information during programming and testing. The command boat controller includes command and status registers coupled to the data bus for receiving command instructions from the microprocessor, a clock generator for generating the necessary timing, and decoding instructions input to the command and status registers. It consists of a state decoder and a state decoder.

Additionally, the command boat controller provides erase and programming algorithms to perform memory erase and programming. The erase algorithm provides the necessary voltages to erase the flash memory cells and then verifies that the memory has been erased. The erase cycle is monitored and repeated with each erase pulse having a predetermined pulse width that is incremented until erasure is complete. However, even if the maximum pulse count is reached, if the memory is not completely erased, an erroneous error will be detected.

Similarly, during memory programming, the algorithm programs each memory location and verifies its contents after programming. The programming cycle is monitored and repeated with each programming pulse having a predetermined pulse width until programming is complete. However, if programming cannot be completed after a predetermined maximum pulse count, a programming error is noted.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Microprocessor control and erasure of programs.

A command boat architecture is described that uses flash memory to perform program verification, erase verification verification, and read modes. In the following description, numerous specific details are set forth, such as specific circuitry and components, in order to provide a thorough understanding of the invention; however, the invention may be practiced without these specific details. It will be obvious to those skilled in the art that this may be done. In other respects, well-known processes, architectures, and circuits have not been described in detail in order not to unnecessarily obscure the present invention.

A preferred embodiment of the present invention is used in conjunction with a particular bipolar single transistor electrically erasable programmable flash memory, also referred to as a flash EPROM. It is a high-density non-volatile flash memory optimized for reprogramming capability under microprocessor control. This particular 7 lash EFR
The OM utilizes state-of-the-art 1.5 μm Complementary Metal Oxide Semiconductor (0MO8) technology providing 32,768×8 bits with 6 μm×6 μm cells fabricated on a 192 ml square board. In the following, two specific
Although a 56-bit flash EFROM is described, it should be understood that other memory sizes and other memory technologies are applicable to the present invention.

The non-volatile flash EPROM of the present invention is based on EPROM technology. The memory cells use a programming mechanism similar to IPROM, but can be erased electrically. Electrical erasing of flash memory is made possible by the use of high quality tunneling oxide beneath the single transistor floating polysilicon gate cell. Flash cells require a 12 volt power supply when erasing and programming. The erase mechanism utilizes Fowler-Nordheimd/Nelling to move electrons from the floating gate to the source junction of the cell. Programming is performed by the standard EPROM method of injecting hot electrons from the drain junction of the cell into the floating gate. The flash EPRQM cells used in the present invention are described in the prior art references cited in the "Prior Art" section of this application.

Direct bin compatibility between flash EPROMs and conventional memory devices is not possible without the use of special circuitry. To maintain bin compatibility between flash memory and conventional gFROM devices, the present invention provides a special command boat architecture that allows in-circuit erasure and in-circuit programming. The command boat architecture of the present invention allows microprocessor control of programming, erasing, program/erase check verification, and read modes while maintaining bin compatibility with conventional IPROM/EEPROM. This special architecture is implemented in circuitry included in the semiconductor chip in which the flash memory is embedded.

Explanation will be made regarding FIG. 1, a Kuratuyu EPROM semiconductor device 10 of the present invention is shown. Address bus 12 couples address bits AO-A14 to address latch 13. Although 15 bits are used to provide one address on address bus 12, the actual number of address bits is arbitrary. Address latch 13 is coupled to X decoder 14 and Y decoder 15. X decoder 14 is coupled to memory array 11 , and Y decoder 15 is coupled to Y gate 4f circuit 16 . Memory array 11 in the preferred embodiment is a 256-bit cell play structure, and X decoder 14
1, the Y decoder 15 performs decoding to access the X (row) addressing of the X-Y matrix of
Perform decoding for Y (column) addressing of the matrix. The configuration of the memory array 11 and its further access through the use of the X decoder 14, Y decoder 15, and column gate 477 circuit 16 is similar to conventional l
It is well known in PROM technology.

Data is transferred to EFRO via an 8-bit bidirectional data bus 20.
In this case, the number of bits of the data bus 20 is arbitrarily selected depending on the circuit configuration. The data bus 20 is coupled to the input/output (Ilo>A sofa 21), and data to be input to the memory array 11 is coupled from the bus 231 via the data latch 22.Reverse button, from the memory array 11 to the data bus 20 Data to be output is coupled from bus 23b to I10 buffer 21 via sense circuit 101, and then output to data bus 20. Input data is also coupled to command boat controller 30 via bus 23a1. Command boat controller 30 further receives external signals WE and CE;
Control signals are provided to address latch 13, data latch 22, erase voltage generator 24, program voltage generator 25, and erase/program check generator 26. External signal CE and pin are chip/output enable logic circuit 2γ
is combined with These data, address and control signals are generated by a microprocessor, such as those commonly used in conjunction with semiconductor memory.

A supply voltage VCC and its return voltage VSS are coupled to the EPROM device 10 and also have a programming voltage value that determines whether the command board controller 30 is enabled to select a read, erase or program function. Voltage VPP is also coupled to device 10. The vPP is coupled to a command boat controller 30, an erase voltage generator 24, a program voltage generator 25, and an erase/program verify generator 26. The generation of these voltages is irrelevant to the practice of the present invention.

Chip/output enable logic circuit 2T is coupled to I10 buffer 21. This circuit 2T is I10 buffer 2
A control signal is supplied to 1. Erase voltage generator 24 is coupled to memory array 11 to provide the necessary voltages to erase memory array 11 simultaneously. The output terminal of program voltage generator 25 is coupled to the program function output terminal of erase/program test generator 26 to X-decoder 14 to provide a test voltage to memory array 11 when the erase/program test function is selected. The X decoder 14 and the Y decoder 151C are coupled to supply a program voltage to the memory array 11 when the memory array 11 is programmed.

A preferred embodiment EPROM device 1 is used to perform in-circuit erasure and programming of the memory array 11.
0 is configured to receive such instructions via data bus 20 from a processor coupled to device 10. Chip enable signal CB should be low whenever EPROM device 10 is to be selected;
is arranged to receive mode commands via data bus 20. The command is sent via the I10 buffer 21 to the command yt.
(-) reaches the controller 30; The command boat controller 30 performs programming, program inspection, and erasure.

Contains six instructions: Erase Verification (Confirmation), Read and Signature Read (special read function to align memory array 11 with appropriate external equipment protocols)
One of the instructions of the ai class (n is the number of data bits) is received from the data bus 2D.

Depending on which command word is received, command boat controller 30 generates control signals to cause appropriate corresponding actions. A specific command is sent to the command boat controller 3.
0, the write enable signal WE1, the chip enable signal CE and the output enable signal OE become E
In order to properly operate the various units of PROM device 10, it controls the generation of various signals from command board controller 730 and chip/output enable logic 2T.

In a preferred embodiment, the command boat controller 3
0 is activated when vPP is at the appropriate voltage value of 12 volts DC. On the other hand, if it is desired to make the command boat controller 30 inactive, vp
The change in the value of p from 12 volts to approximately 5 volts causes the command boat controller 30 to stop operating. V
Every time PP changes to 5 volts, the command boat controller 30 is inactive, so array commands on the data bus 20 destined for the command boat controller 30 are ignored. When vPP is at 5 volts and command boat controller 30 is inactive, lPROM device 10 always functions in read v mode only. The non-operating method of this command boat controller 30 is EPROM
The device 10 is a conventional GPU where 12V voltage does not exist.
oM (or ggpRo used only for read operations)
When used as a direct replacement for g), it was provided on the chip of the device 10 of the preferred embodiment. In such conventional EFROMs, vPP is typically 5 volts, so if EPROM device 10 is used as a direct replacement for a conventional EFROM, device 10 will operate only in read mode. This controller deactivation scheme also completely prevents the contingency of erasing or programming memory when vPP goes to 5 volts.

Explanation will be made regarding FIG. 2. FIG. 2 is a block diagram schematically illustrating the command boat controller 30 of the preferred embodiment. Chip enable signal CE is coupled to control logic 31 and address clock generator 32. Write enable signal WE is coupled as an input to control logic 31. The control logic 31 determines that the chip enable signal CB is E.
Write enable signal WE is coupled to address clock generator 32, state clock generator 33, and command/data clock generator 34 only when PROM device 10 is operated. the output of the state clock generator 33;
The data on data bus 23& is coupled to a status register 35, the output of status register 35 being coupled to a status decoder 36;
The command clock generator 34& is coupled to the command clock generator 34&. The output of command clock generator 34& is coupled to command register 3T. Command register 37 also receives data from data bus 23m, and the output of command register 3T is coupled to status decoder 36. The output of the address clock generator 32 is the first
The data clock generator 34b provides a strobe to the address latch 13 of FIG. 1, and the data clock generator 34b provides a strobe to the data latch 22 of FIG. The output of status decoder 36 is returned to control address clock generator 32 and status register 35. Another output of state decoder 36 is connected to erase voltage generator 24 . shown in FIG. It is supplied to a program voltage generator 25 and an erase/program check generator 26. Either status register 35 provides a feedback signal to command clock generator 341, or command register 37 does not have such feedback capability.

Functions are selected via data bus 23& in write cycles controlled by signals WE and CE.

The contents of the address latch 13 are updated at the falling edge of WE. When the signal wg rises, the instruction is sent to the status register 35.
and either the command register 3T or the data latch 22 is loaded. State decoder 36 decodes the new internal mode and initiates appropriate operation by providing corresponding control signals. state decoder 36 to erase voltage generator 24 . The control line signals to each of the program voltage generator 25 and erase/program check generator 26 are connected to the voltage V
The PPt pressure is supplied to the X decoder 14 and Y decoder 15 or the memory array 11. A test voltage derived from VPP is applied to the word line (via the X-decoder) to ensure program and erase limits during program and erase tests.

3, 9g4 and 5 showing the timing sequences of various signals associated with EPROM device 10.
This will be explained with reference to the figures. FIG. 3 illustrates the read function in which memory array 11 is addressed and data is read from memory array 11 when the output enable signal activates chip/output enable logic 27. Logic circuit 27 then operates the output function of buffer 21.

FIG. 4 shows the timing cycle of the erase operation. Erasing command register 3 in first write cycle 40
7 and status register 35, and writing an erase confirmation code to status register 35 in a second write cycle 41. The erase confirmation code starts erasing at the rising edge of the second write cycle 41 of the signal WE. State decoder 36 initiates a command to erase voltage generator 24 where erase voltage generator 24 applies 12pol Bvpp to the sources of all array cells of memory array 11.
) and ground all word lines. Fowler Q Nordheim tunneling erases all cells of memory array 11 simultaneously. When the erase check code is written to status register 35 and command register 37 in write cycle 42, the erase is completed, the address of the byte to be tested is latched, and the internal erase limit voltage is set up. Here, the microprocessor can access the output of the memory from the accessed address using standard read timing when the signal plane goes low at time 43.

The test procedure is then repeated for all addresses.

Programming is performed in the manner shown in FIG.

Program commands are input to status register 35 and command register 37 during the first cycle 45 of the write enable signal. The second WE psile 46 loads the address latch 13 and data latch 22. second W
A rising edge of EPSILE 46 initiates programming by causing state decoder 36 to generate a control signal to program voltage generator 25. Program voltage generator 25 then applies high voltage vPP to the gate and drain of the addressed cell of memory array 11.

By writing a program check command to the status register 35 and the command register 37 in the third WE psyle 4T,
Programming is completed and internal limit voltages are set to test the newly programmed byte. Again, when the plane goes low at time 48, the addressed byte can be accessed using standard microprocessor read timing.

Next, FIG. 6 will be explained. FIG. 6 is a flowchart illustrating the erasure algorithm utilized by command boat controller 30. During the initial configuration phase, vPP
is applied and every byte has a specific value, in this case OO
H (preconditioning) and the counter is preset to a predetermined initial setting value. Next, an erase set-up command is written, followed by an erase command (
(See timing diagram in Figure 4). During the timeout period during which erasure is performed, an erase check command is written, followed by another predetermined timeout period (6 microseconds in this case).

The data is then read from the memory and a test is performed on the data to determine whether the data has been erased.

If the data has not been erased, the pulse width for erasing the data is incremented by a predetermined value, stored in the TEW counter, and checked for the maximum limit (CUMTE
W and TgW calculations are shown in Figure 6). In the preferred embodiment, the pulse width is incremented to the maximum limit over a cumulative erase time of 10 seconds. After each increment, the sequence repeats again through a write, erase set-up command and a write, erase command.

However, if the data is not erased after a predetermined pulse count (a value of 64 is set in this example), an error message will be written indicating that erasure cannot be performed for that memory cell. . Each time data is read and found to be erased, the address is incremented and the erase test sequence is repeated until the last address is tested. If the final address is verified, a read command is written to the command and status registers to reset them for a read operation;
The erase cycle ends. If no byte is tested as erased, the pulse width TEW is incremented and the erase sequence is repeated. Erase efficiency is also achieved by starting the test cycle from the last erased and tested byte.

Next, reference will be made to FIG. 7, which shows a flowchart of the programming algorithm. The programming cycle begins by applying vPP and initializing the pulse counter. Next, a program setup command is written to the command and status registers, followed by a second write cycle to latch the address and data (see timing diagram in Figure 5).6 Programming is performed at the specified time. After a timeout period of , a program verification command is written. After a further predetermined timeout period (64 μ5 ec in this example), the data is read from the memory in order to verify the programmed data. If the written data does not correspond to the data read from memory, the pulse count is incremented to extend programming time and the write and read sequences are repeated. In the example with 100
As&! The programming time is extended by repeating the pulses up to a maximum pulse count of 25. For each increment of pulse count, a predetermined value, in this case 25
The duration of the programming period is increased until 25 is reached, at which point an error is detected. If the data read is verified as accurate, the address is incremented and the sequence is repeated to write and read data from each of the other addresses. When the last address is reached, an instruction is written to the status and command registers to reset them for read operations. The algorithm in the fs7 diagram is t
! It is also used to load φφ for preconditioning prior to erasure of the c6 diagram.

Although a variety of conventional circuits may be implemented to implement the blocks shown in Figures 8A to 8E,
The figure shows specific circuitry as used in the preferred embodiment to provide the various blocks of FIG. Reference symbols in the figure indicating various blocks in FIG.
Corresponds to the reference numerals in figure E. Furthermore, the reset circuit 50
and page register circuit 51 are shown. The reset circuit 50 is for resetting the command register and status register during power-up or when vPP is 5V. The page register circuit 51 is for controlling page mode addressing of the memory. Furthermore, the control logic circuit 31 is not specifically shown because it basically ANDs the Hirochip enable signal and the write enable signal. The resulting signal is designated CWE.

The preferred embodiment utilizes a series of inverters to provide a delay in generating strobes from address clock generator 32 to the address latches. As used in the particular circuit of the preferred embodiment, command register 37 is comprised of four separate registers R3, R5, R6 and Rγ.

Registers R5, R6 and R7 are used for mode selection and register R3 is used to decode and latch invalid inputs. The status register 35 has two registers. Register R2 is used with feedback control to operate the erase and program status register 2.
1 is used to control the data input flow to the data latch or command register. Command clock generator 34
& data clock generator 34b has the function of generating the non-overlapping clock phases required by the registers and data latches. These clocks control the latching of input data during write cycles to the program data latches, command registers, and status registers.

The address clock generator is responsible for controlling the flow of address information towards the address latches. Status register 35 and command register 3T form the heart of the command boat architecture and receive input from the data human buffer and store data for decoding the operating mode for the chip.

The command command is determined by three data bits for registers 5, 6 and T, and a truth table for determining the operating mode from those bits is shown in FIG. 8E.

The command register tracks single write mode with no feedback from its output terminal and selects entry into multiple write mode. The status register has a feedback path from its output terminal to its input terminal to track the sequential operation of the chip as it passes through the various stages of the multiple write mode.

If the lPROM device 10 is to be made compatible with existing gpRou devices, the write enable signal is multiplexed with the most significant address pin 14. When vPP is 5 volts, the A14/WE bin reads the most significant address bit (A14), which is optionally used to select page mode. However, when the vplx programming voltage (12 volts in this example) is reached, the signal on the A14/WE bin is read as a write enable signal. Therefore, by multiplexing the most significant address bit with the write enable signal, the multiplexing scheme can make the EFROM device 10 of the present invention bin compatible with existing EFROM devices.

Thus, a command boat architecture for programming and erasing flash EPROM/EEPROM has been described.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a 7-lash memory device of the present invention, FIG. 2 is a schematic block diagram of a command boat controller of the present invention, and FIG. 3 is a timing diagram regarding the read cycle of the present invention. , FIG. 4 is a timing diagram for the erase cycle of the present invention, FIG. 5 is a timing diagram for the programming cycle of the present invention, and FIG. 6 is a timing diagram for the erase cycle of the present invention.
A flowchart diagram of the erase cycle of the present invention, FIG.
Flowchart diagrams related to the programming algorithm of the present invention, and FIGS. 8A, 8B, 8C, tgs
Figures D and 8E are schematic diagrams of the command boat controller shown in Figure 2. 10. ...Flash EPROM semiconductor device, 1
1...Memory array, 12...Address bus,
13...address latch, 14...X decoder, 1
5... Y decoder, 20... Bidirectional data bus, 21... Input/output buffer, 22... Data latch, 24... Erase voltage generator, 25...・・・
- Program voltage generator, 26... Erase/program check generator, 27... Chip/output enable logic circuit, 30... Command boat controller, 31
...Control logic, 32...Address clock generator, 33...State clock generator, 34...
・Command clock generator, 34b...-Data clock generator, 35...Status register, 36...Status decoder, 37...Command register CE
II...Chip enable signal, OE...Output enable signal, WE...Write enable signal.

Claims (3)

[Claims] (1) a memory consisting of a plurality of memory cells each having one floating gate, said memory cells arranged in the form of a matrix of rows and columns; coupled to said memory and defining storage locations of said memory; an address bus for accessing; a bidirectional data bus coupled to the memory for transferring data therethrough; and a bidirectional data bus coupled to the data bus for receiving command and command words input to the data bus; a command controller coupled to the command controller and the memory for receiving control signals from the command controller and for acting on the memory: a read signal, an erase signal, a program signal, an erase check signal and a program; Inspection (confirmation)
An electrically erasable programmable read-only storage device formed on a silicon substrate comprising circuit means for generating a signal. (2) a memory consisting of a plurality of memory cells each having one floating gate, said memory cells arranged in the form of a matrix of rows and columns; coupled to said memory and defining storage locations of said memory; an address bus for access; a bidirectional data bus coupled to the memory and for transferring data therethrough; and a bidirectional data bus coupled to the data bus for receiving command and command words input to the data bus; a command controller for switching programming and erasing voltages to the memory according to the selected function, and switching means for switching test (verify) signals to read and test data in the memory; an electrically erasable program formed on a silicon substrate, comprising: circuit means coupled to the command controller and the memory for receiving control signals generated from the command controller in accordance with the command command word; Possible read-only storage. (3) a memory consisting of a plurality of memory cells each having one floating gate, said memory cells arranged in rows and columns, in the form of a matrix; coupled to said memory and defining storage locations of said memory; an address bus for access; a bidirectional data bus coupled to the memory and for transferring data therethrough; coupled to the data bus for receiving command and command words input to the data bus; a plurality of registers for latching the command command; a state decoder for converting the command command; a clock generator for providing clock and timing signals; coupled to the command controller and the memory. an erasable program formed on a silicon substrate, comprising: circuit means for receiving from the command controller a control signal generated in accordance with the command word for erasing and programming the memory; Possible read-only storage.