JPH0210655B2 - - Google Patents

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Publication number
JPH0210655B2
JPH0210655B2 JP57144414A JP14441482A JPH0210655B2 JP H0210655 B2 JPH0210655 B2 JP H0210655B2 JP 57144414 A JP57144414 A JP 57144414A JP 14441482 A JP14441482 A JP 14441482A JP H0210655 B2 JPH0210655 B2 JP H0210655B2
Authority
JP
Japan
Prior art keywords
current
differential
circuit
output
ratio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57144414A
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Japanese (ja)
Other versions
JPS5935526A (en
Inventor
Nobuo Eda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57144414A priority Critical patent/JPS5935526A/en
Publication of JPS5935526A publication Critical patent/JPS5935526A/en
Publication of JPH0210655B2 publication Critical patent/JPH0210655B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は電力系統の母線等を保護する比率差動
継電器に関する。 従来この種の比率差動継電器としては第1図に
示す回路方式が知られている。この第1図におい
て1は電力系統の母線、2−1〜2−nは分岐系
統の電流検出用変流器(以下CTと略称)、3−1
〜3−nは入力装置で以下の要素より構成されて
いる。4,5はトランス、6は抵抗、7は全波整
流回路である。また、8は比率差動継電器で次の
回路要素より構成されている。9はトランス、1
0は全波整流回路、11,12は抵抗、13は入
力信号のレベル検出回路、14は出力リレーであ
る。 次に第1図の従来回路について以下動作を説明
する。まず、入力装置3−1〜3−nに内蔵のト
ランス4は電流検出用CT2−1〜2−nの2次
電流を各々変換し、トランス4の2次出力は全て
並列接続している。今、CT2−1の2次出力を
検出入力とする入力装置3−1内のトランス4の
合成変流比と他の回線のCT2−2〜2−n及び
各々の入力装置のトランス4の合成変流比とが全
回線とも同一である場合にはキルヒホツフの第1
法則により入力装置3−1〜3−nのトランス4
の2次電流合成値(以下差動電流と称する)ID
平常時には零となり、又母線1の外部事故に対し
ても故障電流は母線1を貫通するため零となる。
一方母線1の内部事故時は電源端より母線1の事
故点に向つて電流が流入するのみであるため差動
電流は零ではなくなる。このように母線の内部事
故時と平常時、あるいは外部事故時の差動電流の
相違を検出する方法を一般に差動方式と称してい
る。すなわち、この差動方式の原理が成立するの
はCT2−1〜2−n、又は入力装置のトランス
4の変流比が誤差を生じない領域においてであ
り、大電流域ではCT2−1〜2−n、又はトラ
ンス4が飽和し誤差電流を生じ、適用に問題があ
る。つまり、この場合は外部事故でありながら誤
差差動電流が生じ、リレーが誤差動作するため、
大電流域においてはリレーの検出感度を低下させ
ておき、誤差々動電流を容易に検出しないような
対策を施している。この方法としてCT2−1〜
2−nの2次電流に比例した電圧をトランス5及
び出力抵抗6で導出し、全波整流回路7を介して
各回線の出力電圧を並列合成して得られる出力電
圧(以下抑制電圧と称する)でリレーの検出値を
抑制する。この回路方式を比率差動方式と称し、
原理構成の例は第1図の比率差動継電器8に図示
の如き回路構成をとつている。すなわちトランス
9は差動電流IDを受け全波整流回路10を介して
抵抗11に出力電圧|EO|を発生させる。一方
各入力装置3−1〜3−nより導出された抑制電
圧は抵抗12の両端に電圧|ER|として受け、
差動出力電圧|EO|と抑制出力電圧|ER|は減
算されるように接続して|EO|−|ER|K(K
は定数)をレベル検出器13で判定し、内部事故
時のみ出力リレー14を動作させる。 次に従来方式の動作特性について以下に説明す
る。第2図は第1図に示した従来方式の特性図
で、一般に1端子比率特性と称する。横軸に抑制
量(1端子のCT2次電流に比例した値でITとす
る)、縦軸に差動量IDを取り、抑制量ITを変化さ
せた時のリレー動作の限界差動量IDの軌跡を表わ
し、電流ID、ITはいずれも入力装置の1次入力に
おける値である。直線25はIT=IDであり母線に電
流端が1回線のみ接続された時の抑制量と差動量
の条件である。すなわち抑制量は各回線のCTの
2次電源に比例し、差動量は各回線のCTの2次
電流ベクトル和であるが、1端電源であるため結
局抑制入力量と同一になる。従つて比率差動継電
器8の動作特性としては必ず直線25よりは傾斜の
小さい特性にする必要がある。尚、ここでは特に
詳細に説明はしないが、母線の内部事故でありな
がら流出電流の生じる母線構成もあり、一般に流
入2に対し流出1の比率の事故まで検出できるよ
うになつていなければならない場合もあり、この
条件下では直線25の傾きはID/IT=0.5となる。よ
つてリレーの動作特性26としては傾きID/IT
0.5でなければならず抑制効果としては弱められ
る方向になる。 従来の比率差動継電器は以上のように構成され
ていたので、流出電流のある母線内部事故を検出
させるための抑制力はID/IT0.5とする必要があ
り、あまり抑制力を強大にする事はできず母線外
部事故時の電流検出用CTの飽和による誤差対策
としては性能が劣つている。したがつて極端な
CTの飽和を生じさせないように、CTの容量を充
分大きくとつておく必要があつた。しかし最近の
超々高圧系統においては系統容量の増大で、送電
線容量が大幅に増大し事故時の過渡直流分電流減
衰時間が大きくなり、又リレーの動作も高速を要
求されているため事故発生後1サイクル程度で動
作できるようなものが必要となつている。直流分
を含んだ電流をCTに印加すればCTは極端に飽和
し易すくなる事は周知の通りであり、外部事故時
の送電線保護リレーの後備しや断時間以上の間、
CTを無飽和にして置くとすればCT容量は膨大な
大きさとなるを免れない。又CTに残留磁束があ
りその残留磁束に加えられる方向の事故電流が流
れた場合には、直流分電流の影響とは別の問題と
してCTは事故電流第1波においてすぐ飽和する
ので高速動作形であれば、これで誤動作してしま
うという大きな欠点があつた。 本発明は上記の欠点を除去するためになされた
もので、近年益々比率差動継電器に対する性能要
求がきびしくなつてきている折から、従来形継電
器では性能的に対処の限界に来ていることに鑑
み、超高速でかつ電流検出用CTの飽和に対する
性能を大幅に向上させ、かつCT容量の増大を極
力抑えた高性能、安価な比率差動継電器を提供す
ることを目的とする。 以下、本発明の一実施例を図について説明す
る。第1図と同一の部分は同一の符号をもつて示
した第3図において、15は本発明の比率差動継
電器で第1図に示す従来の比率差動継電器8に相
当する。16はトランス、17は全波整流回路、
18は全波整流回路17の出力を受けこの入力値
が一定値以上の場合にスイツチングするレベル検
出回路でこれらの構成を総称して以下差動要素と
称する。19は抵抗12の出力電圧|ER|が抵
抗11の出力電圧|EO|より一定値以上大きい
場合にスイツチングするレベル検出回路、20は
レベル検出器19が出力を出した場合その信号が
消滅してから時間T1の間信号を継続させるOFF
デイレー回路、21はNOT回路、22はAND回
路でありこれらを総称して以下比率要素と称す
る。尚トランス16の入力IDは従来と同じく差動
量抵抗12の入力|ER|は従来と同じく抑制量
である。 以下、本発明の動作について説明する。トラン
ス16の入力である差動量と抵抗12の入力であ
る抑制量の導出方法は従来と同一であるためここ
では省略する。まず、CT飽和のない単純な正弦
波形電流における母線の内、外部事故について
各々説明する。まず母線の外部事故の場合は従来
方式の動作原理で述べたように差動電流IDは零で
あり、抑制電圧|ER|は事故電流に比例したも
のが発生する。この時比率差動継電器15は差動
電流IDが零のためトランス16の出力はなく、レ
ベル検出器18はスイツチングしないため差動要
素出力23は信号なしの状態である。又、抵抗1
1の出力電圧|EO|も零で抵抗12の出力|ER
|のみが発生しているため|ER|−|EO|>K
(Kは定数)を検出するレベル検出器19はスイ
ツチングしてOFFデイレー回路20の出力は継
続しているが、NOT回路21で信号を反転させ
ているためNOT回路21の出力信号(比率要素
の信号)24は零の状態である。従つて差動要素
信号23、及び比率要素信号24共に零であるた
めAND要素22の出力も零レベルで出力リレー
14は動作しない。 次に母線の内部に事故がある場合には、事故電
流に比例した差動電流IDと抑制電圧|ER|が発生
する事になり差動電流IDが規定値以上あればレベ
ル検出器18はスイツチングして差動要素出力2
3を出力する。又比率要素信号24は抵抗12に
発生する抑制電圧|ER|と、差動動電圧|EO
の演算|ER|−|EO|Kを検出する事になり
電圧|ER|と|EO|の導出条件に一定の比率を
持たせておくことにより内部事故時は|EO|>
|ER|となる。従つてレベル検出器19はスイ
ツチングすることもなく、NOT要素21の出力
信号24はハイレベルとなるためAND要素22
の入力信号条件が成立して出力リレーは動作す
る。以上の動作を特性図で図示すると第4図の如
く表わされる。すなわち第4図はすでに説明した
従来の特性図第2図と同様の表現方法で示した1
端子比率特性図であり、直線25は1端子電源にお
ける母線の内部事故時の軌跡であり、流出電流の
ある内部事故時では傾きID/IT=0.5までを考慮し
ておく必要がある事は前述の通りである。動作特
性27は差動要素の特性であり、第3図のレベル
検出器18が差動電流IDを規定値以上で検出する
ことを表わしている。また、動作特性28は比率
要素の特性であり、第3図のレベル検出器19が
抑制電圧|ER|∝ITと差動電圧|EO|∝ηID(ηは
定数)の演算において|ER|−|E0|=IT−ηID
≧Kを示すものである。尚、動作特性28は原点
を起点に傾斜η≒IT/IDとなるものであるが、レ
ベル検出器19の最小検出値条件によりITが規定
値IT1以上で動作するようにしているが、本発明
の範囲ではないので詳述は避ける。母線の内部事
故時は直線25の線上、又はこれより傾きの大きい
方向の範囲の直線上に抑制電流ITと差動電流の関
係はあるため、母線内部事故時における差動要素
の特性27及び比率要素の特性28は直線25の傾
き以下にして置けばよい事になる。尚外部事故時
において電流検出器CTの飽和を生じ誤差の差動
電流を生じた場合には、その飽和の状況によつて
は差動要素の動作特性27の限界以上になり第3
図のレベル検出器8がスイツチングする可能性が
ある。この場合における出力リレー14を誤動作
させない方策が比率要素の動作特性28で、抑制
電流IDの関係を第4図の動作特性28の斜線内に
保持する限りは比率特性が作動しAND要素22
の出力をロツクするようにしている。 次に本発明の目的である電流検出器CT飽和の
著しい外部事故時について第5図を用いて動作原
理を説明する。波形IFは事故点に流れる電流流出
波形の一例で実際の事故電流波形はCTの飽和に
対して最も過酷な条件下にある。すなわち、事故
発生時に過渡直流分電流が交流分電流ピーク値に
対し100%重畳したケースであり交流分電流を
IFP、直流分電流の減衰時定数をTとすれば、事
故電流
The present invention relates to a ratio differential relay for protecting busbars, etc. of a power system. A circuit system shown in FIG. 1 is conventionally known as this type of ratio differential relay. In this Figure 1, 1 is the bus bar of the power system, 2-1 to 2-n are the current detection current transformers (hereinafter abbreviated as CT) of the branch system, and 3-1
3-n is an input device, which is composed of the following elements. 4 and 5 are transformers, 6 is a resistor, and 7 is a full-wave rectifier circuit. Further, 8 is a ratio differential relay, which is composed of the following circuit elements. 9 is transformer, 1
0 is a full-wave rectifier circuit, 11 and 12 are resistors, 13 is an input signal level detection circuit, and 14 is an output relay. Next, the operation of the conventional circuit shown in FIG. 1 will be explained below. First, the transformers 4 built into the input devices 3-1 to 3-n convert the secondary currents of the current detection CTs 2-1 to 2-n, respectively, and the secondary outputs of the transformers 4 are all connected in parallel. Now, the composite current transformation ratio of the transformer 4 in the input device 3-1 which uses the secondary output of CT2-1 as the detection input, and the composite of the transformer 4 of CT2-2 to 2-n of other lines and each input device. If the current transformation ratio is the same for all lines, Kirchhoff's first
According to the law, the transformers 4 of input devices 3-1 to 3-n
The secondary current composite value (hereinafter referred to as differential current) I D is zero under normal conditions, and even in the event of an external fault on the bus 1, the fault current passes through the bus 1 and becomes zero.
On the other hand, when an internal fault occurs on the bus 1, the current only flows from the power supply end toward the fault point on the bus 1, so the differential current is not zero. The method of detecting the difference in the differential currents in the case of an internal fault on the bus bar, in a normal state, or in the case of an external fault is generally called a differential method. In other words, the principle of this differential method is valid in the area where the current transformation ratio of CT2-1 to 2-n or the transformer 4 of the input device does not cause an error, and in the large current area, CT2-1 to 2-n -n, or the transformer 4 is saturated and an error current is generated, causing a problem in application. In other words, in this case, even though it is an external fault, an error differential current is generated and the relay operates with an error, so
Measures are taken to reduce the detection sensitivity of the relay in the large current range, and to prevent erroneous dynamic current from being detected easily. As this method, CT2-1~
A voltage proportional to the secondary current of 2-n is derived by a transformer 5 and an output resistor 6, and an output voltage (hereinafter referred to as suppression voltage) obtained by parallel combining the output voltages of each line via a full-wave rectifier circuit 7. ) to suppress the relay detection value. This circuit system is called ratio differential system.
An example of the principle structure is a ratio differential relay 8 in FIG. 1 having a circuit structure as shown. That is, the transformer 9 receives the differential current ID and causes the resistor 11 to generate an output voltage |E O | via the full-wave rectifier circuit 10. On the other hand, the suppression voltage derived from each input device 3-1 to 3-n is received as a voltage |E R | across the resistor 12,
The differential output voltage |E O | and the suppressed output voltage |E R | are connected so that they are subtracted, so that |E O |−|E R |K(K
is a constant) is determined by the level detector 13, and the output relay 14 is operated only in the event of an internal accident. Next, the operating characteristics of the conventional system will be explained below. FIG. 2 is a characteristic diagram of the conventional method shown in FIG. 1, which is generally referred to as a one-terminal ratio characteristic. The horizontal axis shows the suppression amount (I T is a value proportional to the CT secondary current of one terminal), and the vertical axis shows the differential amount I D , and the limit differential of relay operation when the suppression amount I T is changed. It represents the locus of the quantity I D and the currents I D and I T are both values at the primary input of the input device. The straight line 25 represents the conditions for the amount of suppression and the amount of differential when I T =I D and only one current end is connected to the bus bar. That is, the amount of suppression is proportional to the secondary power supply of the CT of each line, and the differential amount is the sum of the secondary current vectors of the CT of each line, but since it is a single-end power supply, it ends up being the same as the amount of suppression input. Therefore, the operating characteristics of the ratio differential relay 8 must be such that the slope is smaller than that of the straight line 25. Although it will not be explained in detail here, there are some busbar configurations in which outflow current occurs even though it is an internal fault in the busbar, and in general, it is necessary to be able to detect faults with a ratio of 2 inflows to 1 outflow. Under this condition, the slope of straight line 25 is I D / IT = 0.5. Therefore, the operating characteristic 26 of the relay is the slope I D /I T
It must be 0.5, which means that the suppressing effect will be weakened. Conventional ratio differential relays were configured as described above, so the suppression force must be I D /I T 0.5 to detect a fault inside the bus with outflow current, so it is not recommended to make the suppression force too strong. It is not possible to do so, and the performance is poor as a countermeasure against errors caused by saturation of the current detection CT in the event of an external fault on the bus bar. therefore extreme
It was necessary to keep the capacity of the CT sufficiently large so as not to cause saturation of the CT. However, in recent ultra-high voltage systems, the capacity of the transmission line has increased significantly due to the increase in system capacity, which has increased the decay time of transient DC current in the event of an accident, and relays are required to operate at high speed. There is a need for something that can operate in about one cycle. It is well known that if a current containing a DC component is applied to a CT, the CT becomes extremely susceptible to saturation.
If the CT is left unsaturated, the CT capacity will inevitably become enormous. In addition, if there is residual magnetic flux in the CT and a fault current flows in the direction that is added to the residual magnetic flux, a problem other than the influence of DC component current is that the CT will saturate immediately at the first wave of fault current, so high-speed operation type If so, this would have caused a major drawback in that it would malfunction. The present invention was made in order to eliminate the above-mentioned drawbacks, and as performance requirements for ratio differential relays have become increasingly strict in recent years, conventional relays have reached their performance limits. In view of this, the object of the present invention is to provide a high-performance, inexpensive ratio differential relay that is ultra-high-speed, greatly improves the saturation performance of a current detection CT, and minimizes the increase in CT capacity. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In FIG. 3, the same parts as in FIG. 1 are designated by the same reference numerals. Reference numeral 15 denotes a ratio differential relay of the present invention, which corresponds to the conventional ratio differential relay 8 shown in FIG. 16 is a transformer, 17 is a full wave rectifier circuit,
Reference numeral 18 denotes a level detection circuit which receives the output of the full-wave rectifier circuit 17 and switches when the input value is above a certain value, and these components are collectively referred to as differential elements hereinafter. 19 is a level detection circuit that switches when the output voltage |E R | of the resistor 12 is larger than the output voltage |E O | of the resistor 11 by more than a certain value; 20, when the level detector 19 outputs an output, the signal disappears; OFF to continue the signal for a time T 1 after
The delay circuit, 21 is a NOT circuit, and 22 is an AND circuit, which will be collectively referred to as a ratio element hereinafter. The input I D of the transformer 16 is the same as the conventional one, and the input |E R | of the differential resistor 12 is the suppression amount as the conventional one. The operation of the present invention will be explained below. The method for deriving the differential amount, which is the input to the transformer 16, and the suppression amount, which is the input to the resistor 12, is the same as the conventional method, and therefore will not be described here. First, we will explain each external fault among the busbars in a simple sinusoidal current without CT saturation. First, in the case of an external fault on the busbar, the differential current I D is zero, as described in the operating principle of the conventional system, and a suppression voltage |E R | proportional to the fault current occurs. Since the differential current ID of the duty ratio differential relay 15 is zero, there is no output from the transformer 16, and since the level detector 18 does not switch, the differential element output 23 is in a state of no signal. Also, resistance 1
The output voltage of resistor 1 | E O | is also zero and the output of resistor 12 | E R
|E R |−|E O |>K
(K is a constant) is switched, and the output of the OFF delay circuit 20 continues, but since the signal is inverted by the NOT circuit 21, the output signal of the NOT circuit 21 (of the ratio element) is switched. The signal) 24 is in a zero state. Therefore, since both the differential element signal 23 and the ratio element signal 24 are zero, the output of the AND element 22 is also at zero level, and the output relay 14 does not operate. Next, if there is a fault inside the bus, a differential current I D and a suppression voltage |E R | proportional to the fault current will occur, and if the differential current I D exceeds the specified value, a level detector will be detected. 18 is switched and differential element output 2
Outputs 3. Further, the ratio element signal 24 is the suppression voltage |E R | generated in the resistor 12 and the differential voltage |E O |
Calculation of |E R |−|E O |K is detected, and by keeping a certain ratio in the derivation conditions for voltage |E R | and |E O |, in the event of an internal accident, |E O | >
|E R | becomes. Therefore, the level detector 19 does not switch, and the output signal 24 of the NOT element 21 becomes high level, so the AND element 22
The input signal condition is satisfied and the output relay operates. The above operation is illustrated in a characteristic diagram as shown in FIG. In other words, Fig. 4 shows 1 expressed in the same way as the conventional characteristic diagram Fig.
This is a terminal ratio characteristic diagram, and the straight line 25 is the locus in the event of an internal fault on the bus bar in a one-terminal power supply, and it is necessary to consider the slope up to I D / I T = 0.5 in the event of an internal fault with outflow current. is as described above. The operating characteristic 27 is a characteristic of the differential element, and indicates that the level detector 18 in FIG. 3 detects the differential current ID above a specified value. In addition, the operating characteristic 28 is a characteristic of a ratio element , and the level detector 19 in FIG . |E R |−|E 0 |=I T −ηI D
≧K. Note that the operating characteristic 28 is such that the slope η≒I T /I D starts from the origin, but the minimum detection value condition of the level detector 19 is such that I T operates at a specified value I T1 or more. However, since it is not within the scope of the present invention, a detailed description will be omitted. At the time of an internal fault in the bus bar, the relationship between the suppression current I T and the differential current is on the straight line 25 or on a straight line in a direction with a larger slope. The characteristic 28 of the ratio element should be set below the slope of the straight line 25. In addition, if the current detector CT is saturated during an external fault and an erroneous differential current is generated, depending on the saturation situation, it may exceed the limit of operating characteristics 27 of the differential element and the third
There is a possibility that the level detector 8 shown in the figure may switch. The measure to prevent the output relay 14 from malfunctioning in this case is the operating characteristic 28 of the ratio element.As long as the relationship between the suppression current I D is maintained within the hatched area of the operating characteristic 28 in FIG.
The output is locked. Next, the principle of operation will be explained with reference to FIG. 5 in the case of an external accident in which the current detector CT saturation is significant, which is the object of the present invention. The waveform I F is an example of a current outflow waveform flowing to a fault point, and the actual fault current waveform is under the most severe conditions for CT saturation. In other words, this is a case where the transient DC current is 100% superimposed on the peak value of the AC current when an accident occurs, and the AC current is
If I FP and the decay time constant of the DC component current are T, then the fault current is

【式】で表わされ る。波形I1は外部事故端のCT2次電流の波形例で
あり、この外部事故端(流出端)CTの1次電流
としては波形IFで、大きさは事故電流の大きさと
同一になるため最も飽和しやすい条件にある。波
形の斜線部がCT2次電流波形であり、点線はCT
が飽和してない時を表わしている。波形I2は誤差
の差動電流であり、きびしい条件として流入端
CTが不飽和で、流出端(事故端)CTのみが波形
I1のように飽和したとすれば、誤差差動電流I2
しては波形IFと波形I1の差が発生することになる
ので斜線に示すような波形となる。この時第3図
の比率差動継電器15の入力としては動作入力ID
は第5図の波形I2が印加され、又抑制入力|ER
としては波形|I1|が印加されるので第3図の抵
抗11,12に発生する電圧|EO|、及び|ER
|は結局|EO|∝|I2|、|ER|∝|I1|となる
ため、電圧|ER|−|EO|の波形はK1|I1|−
K2|I2|の波形と同一になる。尚、レベル検出器
19は|ER|−|E0|≧Kの時のみスイツチン
グするようになつており、|EO|>|ER|では定
常時の出力形態となるようにしているため、レベ
ル検出器19の入力としては|ER|−|EO
0の範囲の入力波形と大きさのみが問題となる。
この|ER|−|EO|=K1|I1|−K2|I2|の波
形は第5図に示す如く、CTが飽和して差動電流
I2が発生しだすと消滅するがCT飽和に達するま
では電流I1に比例して出力が発生する。すなわ
ち、事故発生後、第1波においてはCTの残留磁
束と事故電流により発生する磁束の和がCTの飽
和磁束に達するまでの時間t1間はCT無飽和であ
り、CT2次電流I1は1次電流IFに比例して発生
し、誤差々動電流I2は生じないためK1|I1|−K2
|I2|は電流I1に比例している。次に第2波は事
故電流IFの直流分電流の減衰時定数Tに大きく左
右されるが、負波側に時間t2分だけ生じたとすれ
ば、負波分電流の大きさ(面積に比例)した値が
第2波の正弦分として時間t3の間発生することに
なり、CTはt2+t3の間無飽和期間として波形I1
t2+t3間のものがK1|I1|−K2|I2|に生じるこ
とになる。レベル検出器19の入力はK1|I1|−
K2|I2|であるため、レベル検出器19の出力信
号25は第5図に示す如く第1波の時間t1及び第
2波の時間t2+t3において、K1|I1|−K2|I2
の大きさが規定値以上に達した範囲においてスイ
ツチングして出力パルスを発生し、これをOFF
デイレー回路20でT1時間信号を引延すため
NOT回路21の信号24は第5図の如く連続信
号となる。この引延し時間T1は直流分電流の減
衰時間Tが長く、第2波において電流I1のt2+t3
が短かく、K1|I1|−K2|I2|の大きさが小さい
ため第3図の信号25の第2パルスが発生しない
場合は時間T1を長くして第3波、又は第4波に
よるパルスまで引延せばよい。 以上のようにCTの残留磁束によりCT2次電流
が第1波で著しく飽和し、又直流分電流により第
2波以降も引続き飽和が大きく生じても、比率要
素のレベル検出器19の検出値及びOFFデイレ
ー回路20の信号引延し時間T1を適宜設定する
事により対策は充分可能となる。 尚、第5図は外部事故時における波形であるが
内部事故時についてもCTが著しく飽和した場合
には差動電流が事故発生と同時に生じ、かつ差動
電流が各電源端CTの2次電流和であるため、必
ず各端CT2次電流よりは大きくなるため|EO
>|ER|となりレベル検出器19が検出する事
はあり得ない。 以上のように本発明は内部事故時と外部事故時
におけるCT飽和による2次電流波形と誤差差動
電流波形の相違に着目し、極端なCT飽和に対し
ても確実に内・外部事故の判別が可能な比率要素
を設けることにより誤動作防止を図つたので、継
電器の性能を向上させる事により信頼性が大幅に
向上し、併せてCTの小形化と低コスト化に極め
て顕著な効果を奏するものである。
It is represented by [Formula]. Waveform I 1 is an example of the waveform of the CT secondary current at the external fault end. The primary current of this external fault end (outflow end) CT is waveform I F , and its magnitude is the same as that of the fault current, so it is the most Conditions are such that it is easy to become saturated. The shaded part of the waveform is the CT secondary current waveform, and the dotted line is the CT
It represents the time when is not saturated. The waveform I2 is the error differential current, and the severe condition is that the inflow end
CT is unsaturated and only the outflow end (fault end) CT has a waveform
If it is saturated like I 1 , a difference between the waveform IF and the waveform I 1 will occur as the error differential current I 2 , resulting in a waveform as shown by diagonal lines. At this time, the input of the ratio differential relay 15 in Fig. 3 is the operation input I D
The waveform I 2 shown in Fig. 5 is applied, and the suppression input |E R |
Since the waveform |I 1 | is applied, the voltages generated across the resistors 11 and 12 in FIG. 3 are |E O | and |E R
| eventually becomes |E O |∝|I 2 |, |E R |∝|I 1 |, so the waveform of the voltage |E R |−|E O | is K 1 |I 1 |−
The waveform is the same as that of K 2 |I 2 |. The level detector 19 is designed to switch only when |E R |−|E 0 |≧K, and when |E O |>|E R |, the output mode is set to a steady state. Therefore, the input to the level detector 19 is |E R |−|E O |
Only input waveforms and magnitudes in the zero range matter.
As shown in Figure 5, the waveform of |E R |−|E O |=K 1 |I 1 |−K 2 |I 2 |
Once I 2 starts to generate, it disappears, but until CT saturation is reached, an output is generated in proportion to the current I 1 . That is, in the first wave after an accident occurs, the CT is unsaturated during the time t 1 until the sum of the residual magnetic flux of the CT and the magnetic flux generated by the fault current reaches the saturated magnetic flux of the CT, and the CT secondary current I 1 is Since it occurs in proportion to the primary current I F and no error fluctuation current I 2 occurs, K 1 | I 1 | −K 2
|I 2 | is proportional to the current I 1 . Next, the second wave is largely influenced by the decay time constant T of the DC component of the fault current I F , but if it occurs on the negative wave side for a time t 2 minutes, the magnitude of the negative wave component (proportional) value is generated during time t 3 as the sine component of the second wave, and CT is the non-saturation period of waveform I 1 during t 2 + t 3 .
Something between t 2 + t 3 will occur at K 1 |I 1 |−K 2 |I 2 |. The input of the level detector 19 is K 1 | I 1 | −
Since K 2 |I 2 |, the output signal 25 of the level detector 19 is K 1 |I 1 | at time t 1 of the first wave and time t 2 +t 3 of the second wave, as shown in FIG . −K 2 |I 2
generates an output pulse by switching in the range where the magnitude of
To delay the signal for T 1 hour with delay circuit 20
The signal 24 of the NOT circuit 21 becomes a continuous signal as shown in FIG. This extension time T 1 is a long decay time T of the DC component current, and in the second wave, the current I 1 is t 2 + t 3
is short and the magnitude of K 1 |I 1 |−K 2 |I 2 | is small, so if the second pulse of signal 25 in FIG. It is sufficient to extend the pulse to the fourth wave. As described above, even if the CT secondary current is significantly saturated in the first wave due to the residual magnetic flux of the CT, and even if saturation continues to be large in the second wave and subsequent waves due to the DC component current, the detection value of the level detector 19 of the ratio element and A sufficient countermeasure can be taken by appropriately setting the signal extension time T1 of the OFF delay circuit 20. Figure 5 shows the waveform at the time of an external fault, but even in the case of an internal fault, if the CT is significantly saturated, a differential current will be generated at the same time as the fault occurs, and the differential current will be the secondary current of the CT at each power supply terminal. Because it is the sum, it is always larger than the CT secondary current at each end | E O |
>|E R |, so it is impossible for the level detector 19 to detect it. As described above, the present invention focuses on the difference between the secondary current waveform and error differential current waveform due to CT saturation at the time of internal fault and external fault, and reliably distinguishes between internal and external faults even in the case of extreme CT saturation. By providing a ratio element that can be used to prevent malfunctions, reliability is greatly improved by improving the performance of the relay, and this also has an extremely significant effect on reducing the size and cost of CTs. It is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の比率差動継電器の原理を示すブ
ロツク構成図、第2図は第1図の比率差動継電器
の比率特性図、第3図は本発明の一実施例を示す
比率差動継電器の原理を示すブロツク構成図、第
4図は第3図の比率差動継電器の比率特性図、第
5図は本発明の比率差動継電器の原理を説明する
波形図である。 1……母線、2−1〜2−n……CT、3−1
〜3−n……入力装置、4,5,9,16……ト
ランス、6,11,12……抵抗、7,10,1
7……全波整流回路、8,15……比率差動継電
器、13,18,19……レベル検出器、14…
…出力リレー、20……OFFデイレー回路、2
1……NOT回路、22……AND回路、23……
差動要素の出力信号、25……比率要素の信号。
なお、図中同一符号は同一又は相当部分を示す。
Fig. 1 is a block configuration diagram showing the principle of a conventional ratio differential relay, Fig. 2 is a ratio characteristic diagram of the ratio differential relay shown in Fig. 1, and Fig. 3 is a ratio differential relay showing an embodiment of the present invention. 4 is a block diagram showing the principle of the relay, FIG. 4 is a ratio characteristic diagram of the ratio differential relay of FIG. 3, and FIG. 5 is a waveform diagram illustrating the principle of the ratio differential relay of the present invention. 1... Bus line, 2-1 to 2-n... CT, 3-1
~3-n...Input device, 4,5,9,16...Transformer, 6,11,12...Resistor, 7,10,1
7... Full wave rectifier circuit, 8, 15... Ratio differential relay, 13, 18, 19... Level detector, 14...
...Output relay, 20...OFF delay circuit, 2
1...NOT circuit, 22...AND circuit, 23...
Output signal of differential element, 25... Signal of ratio element.
Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 1 電力系統の複数の分岐電流を変流器によつて
検出し、前記検出された変流器の2次電流をベク
トル合成して得る差動量を導出する電流差動量導
出回路と、前記複数の変流器2次電流の絶対値の
最大、または絶対値の和に比例した抑制量を導出
する電流抑制量導出回路と、前記電流差動量導出
回路の出力信号を検出する第1レベル検出要素
と、前記電流抑制量導出回路出力の瞬時値と前記
電流差動量導出回路出力の絶対値の瞬時値を比較
し、抑制量の方が大なる時に出力信号を発生する
レベル検出回路と、前記レベル検出回路の出力信
号を所定時間引延ばすOFFデイレー回路とを含
む第2レベル検出要素とを備え、前記第1レベル
検出要素の出力信号を前記第2レベル検出要素の
出力で否定するように構成したことを特徴とする
比率差動継電器。
1. A current differential amount deriving circuit that detects a plurality of branch currents in a power system using a current transformer and derives a differential amount obtained by vector-synthesizing the detected secondary currents of the current transformers; a current suppression amount derivation circuit that derives a suppression amount proportional to the maximum absolute value or the sum of the absolute values of the plurality of current transformer secondary currents; and a first level that detects an output signal of the current differential amount derivation circuit. a detection element; a level detection circuit that compares the instantaneous value of the output of the current suppression amount deriving circuit with the instantaneous value of the absolute value of the output of the current differential amount deriving circuit, and generates an output signal when the suppression amount is larger; , a second level detection element including an OFF delay circuit that extends the output signal of the level detection circuit for a predetermined time, and the output signal of the first level detection element is negated by the output of the second level detection element. A ratio differential relay characterized in that it is configured as follows.
JP57144414A 1982-08-18 1982-08-18 Ratio differential relay Granted JPS5935526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57144414A JPS5935526A (en) 1982-08-18 1982-08-18 Ratio differential relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57144414A JPS5935526A (en) 1982-08-18 1982-08-18 Ratio differential relay

Publications (2)

Publication Number Publication Date
JPS5935526A JPS5935526A (en) 1984-02-27
JPH0210655B2 true JPH0210655B2 (en) 1990-03-09

Family

ID=15361614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57144414A Granted JPS5935526A (en) 1982-08-18 1982-08-18 Ratio differential relay

Country Status (1)

Country Link
JP (1) JPS5935526A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2567634B2 (en) * 1987-11-17 1996-12-25 三洋電機株式会社 RDS receiver

Also Published As

Publication number Publication date
JPS5935526A (en) 1984-02-27

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