JPH02106729U - - Google Patents
Info
- Publication number
- JPH02106729U JPH02106729U JP1989016031U JP1603189U JPH02106729U JP H02106729 U JPH02106729 U JP H02106729U JP 1989016031 U JP1989016031 U JP 1989016031U JP 1603189 U JP1603189 U JP 1603189U JP H02106729 U JPH02106729 U JP H02106729U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock pulse
- pulse
- sawtooth wave
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000630 rising effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案によるクロツクパルス位相調整
回路の実施例を示す回路図、第２図は第１図回路
の動作を説明するための波形図、第３図は従来の
クロツクパルス位相調整回路の一例を示す回路図
である。
１，３１……クロツクパルス入力端子、２，３
……モノステーブル・マルチバイブレータ、４，
８，１２，１６，３３，３５……抵抗器、５，１
３，４４……トランジスタ、６，１４，２１，２
３，４２……基準電圧、７，１５，３８，３９…
…コンデンサ、９，１７……演算増幅器、１０，
１１，１８，１９，３６，３７……電源電圧、２
０，２２，４３……比較器、２４，２５……フリ
ツプフロツプ、２６，２７，４４……クロツクパ
ルス出力端子、３２……論理ゲート、４０……コ
イル、４１……可変抵抗器。
Fig. 1 is a circuit diagram showing an embodiment of the clock pulse phase adjustment circuit according to the present invention, Fig. 2 is a waveform diagram for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is an example of a conventional clock pulse phase adjustment circuit. FIG. 1, 31...Clock pulse input terminal, 2, 3
...Monostable multivibrator, 4,
8, 12, 16, 33, 35...Resistor, 5, 1
3, 44...transistor, 6, 14, 21, 2
3, 42...Reference voltage, 7, 15, 38, 39...
... Capacitor, 9, 17 ... Operational amplifier, 10,
11, 18, 19, 36, 37...Power supply voltage, 2
0, 22, 43... Comparator, 24, 25... Flip-flop, 26, 27, 44... Clock pulse output terminal, 32... Logic gate, 40... Coil, 41... Variable resistor.
Claims (1)
クパルスの位相調整回路において、入力クロツク
パルスと同じ周期で、それぞれ位相の異なる２つ
ののこぎり波を発生するのこぎり波発生回路と、
前記のこぎり波発生回路の第１のこぎり波と可変
可能な第１の基準電圧源からの基準電圧とを比較
して第１のパルスを出力する第１の比較回路と、
前記のこぎり波発生回路の第２ののこぎり波と可
変可能な第２の基準電圧源からの基準電圧とを比
較して第２のパルスを出力する第２の比較回路と
、前記第１の比較回路のパルス出力の立ち上がり
で出力クロツクパルスを立ち上げ、前記第２の比
較回路のパルス出力の立ち上がりで出力クロツク
パルスを立ち下げることにより前記入力クロツク
パルスと任意の位相差およびデユーテイ比を持つ
出力クロツクパルスを発生する回路とから構成し
たことを特徴とするクロツクパルス位相調整回路
。 In a clock pulse phase adjustment circuit used in a digital signal processing circuit, etc., a sawtooth wave generation circuit generates two sawtooth waves having the same period as an input clock pulse but each having a different phase;
a first comparison circuit that compares the first sawtooth wave of the sawtooth wave generation circuit with a reference voltage from a variable first reference voltage source and outputs a first pulse;
a second comparison circuit that compares the second sawtooth wave of the sawtooth wave generation circuit with a reference voltage from a variable second reference voltage source and outputs a second pulse; and the first comparison circuit. A circuit that generates an output clock pulse having an arbitrary phase difference and duty ratio from the input clock pulse by raising the output clock pulse at the rising edge of the pulse output of the second comparator circuit and lowering the output clock pulse at the rising edge of the pulse output of the second comparator circuit. A clock pulse phase adjustment circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989016031U JPH0731625Y2 (en) | 1989-02-14 | 1989-02-14 | Clock pulse phase adjustment circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989016031U JPH0731625Y2 (en) | 1989-02-14 | 1989-02-14 | Clock pulse phase adjustment circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02106729U true JPH02106729U (en) | 1990-08-24 |
| JPH0731625Y2 JPH0731625Y2 (en) | 1995-07-19 |
Family
ID=31228606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989016031U Expired - Lifetime JPH0731625Y2 (en) | 1989-02-14 | 1989-02-14 | Clock pulse phase adjustment circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0731625Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57109638U (en) * | 1980-12-24 | 1982-07-06 | ||
| JPS6043917A (en) * | 1983-08-22 | 1985-03-08 | Fujitsu Ltd | Clock phase adjusting circuit |
-
1989
- 1989-02-14 JP JP1989016031U patent/JPH0731625Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57109638U (en) * | 1980-12-24 | 1982-07-06 | ||
| JPS6043917A (en) * | 1983-08-22 | 1985-03-08 | Fujitsu Ltd | Clock phase adjusting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0731625Y2 (en) | 1995-07-19 |
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