JPH02107076U - - Google Patents
Info
- Publication number
- JPH02107076U JPH02107076U JP1475489U JP1475489U JPH02107076U JP H02107076 U JPH02107076 U JP H02107076U JP 1475489 U JP1475489 U JP 1475489U JP 1475489 U JP1475489 U JP 1475489U JP H02107076 U JPH02107076 U JP H02107076U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- output
- shifter
- pass filter
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Landscapes
- Complex Calculations (AREA)
Description
第１図は本考案に係るＦＦＴアナライザの一実
施例を示すブロツク図、第２図は第１、第２のメ
モリのデータの格納状態を示す図、第３図はパワ
ースペクトルの例、第４図は本考案の他の実施例
を示すブロツク図、第５図は従来のＦＦＴアナラ
イザの構成図である。
１……ローパスフイルタ、２……ＡＤ変換部、
４……演算部、１０……第１のメモリ、１１……
シフタ、１２……第２のメモリ、１１１……発振
器、１１２，１１３，２１……乗算器、２０……
マルチプレクサ、１２１，１２２……メモリ。
FIG. 1 is a block diagram showing one embodiment of the FFT analyzer according to the present invention, FIG. 2 is a diagram showing the storage state of data in the first and second memories, FIG. 3 is an example of a power spectrum, and FIG. The figure is a block diagram showing another embodiment of the present invention, and FIG. 5 is a block diagram of a conventional FFT analyzer. 1...Low pass filter, 2...AD conversion section,
4... Arithmetic unit, 10... First memory, 11...
Shifter, 12... Second memory, 111... Oscillator, 112, 113, 21... Multiplier, 20...
Multiplexer, 121, 122...memory.
Claims (1)
のローパスフイルタの出力をデジタル信号に変換
するＡＤ変換部と、このＡＤ変換部の出力が格納
される第１のメモリと、前記入力信号に関連する
信号を所定の周波数だけ周波数シフトするシフタ
と、このシフタの出力が格納される第２のメモリ
と、この第２のメモリまたは前記第１のメモリに
格納されたデータに基づいて高速フーリエ変換を
行う演算部とを有し、これらのフーリエ変換結果
を合成して最終的な変換結果を求めるようにした
ことを特徴とするＦＦＴアナライザ。 a low-pass filter to which an input signal is input; an AD converter that converts the output of the low-pass filter into a digital signal; a first memory that stores the output of the AD converter; and a first memory that stores a signal related to the input signal. A shifter that shifts the frequency by a predetermined frequency, a second memory in which the output of this shifter is stored, and an arithmetic unit that performs fast Fourier transform based on the data stored in the second memory or the first memory. An FFT analyzer characterized in that the FFT analyzer has the following: and is configured to synthesize these Fourier transform results to obtain a final transform result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1475489U JPH02107076U (en) | 1989-02-10 | 1989-02-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1475489U JPH02107076U (en) | 1989-02-10 | 1989-02-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02107076U true JPH02107076U (en) | 1990-08-24 |
Family
ID=31226236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1475489U Pending JPH02107076U (en) | 1989-02-10 | 1989-02-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02107076U (en) |
-
1989
- 1989-02-10 JP JP1475489U patent/JPH02107076U/ja active Pending
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