JPH02107982A - Test circuit of integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of terminals of an integrated circuit by providing a logic means for setting an actual operation state or a test operation state in accordance with a signal level impressed on a clock input terminal. CONSTITUTION:A test state is maintained by setting a voltage level of a signal inputted to a clock input terminal 1 at a threshold value of a gate 4 for selection of a test mode or below. As for an actual operation state, the voltage level of the signal inputted to the terminal 1 operates beyond the threshold value of the gate 4 and consequently D-type flip-flops 11 and 12 operate so that the test state be changed to the actual operation state. By a method wherein the signal level impressed on the terminal 1 is made to be different in the test state from that in the actual operation state and a function of judging the signal level is provided, in this way, selection of the test state and the actual operation state can be conducted and, accordingly, the number of terminals can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit test circuit that efficiently tests the logic circuit operation of an integrated circuit having a clock input terminal.

[Conventional technology]

Conventionally, there has been a test circuit for integrated circuits as shown in FIG. In the figure, 1 is a clock input terminal, 2 is a test mode selection input terminal, 3 is a clock input gate, 4 is a test mode selection gate, 5 is an inverter circuit, 6 -
8 is a NAND circuit configuring the data selection function; 21
.about.2n is a T-type flip-prop that constitutes a branching stage.

Next, the operation will be explained.

When testing an integrated circuit having a large number of branching stages as shown in FIG. 2 under actual operating conditions, the test time may become very long. Therefore, it is common to have a test mode selection input terminal 2.

During actual operation, by setting the test mode selection input terminal 2 to %L', the signal input from the clock input terminal l is divided by the division stage composed of T-type flip-flops 21 to 2n, and its frequency is divided. The signal is NAND circuit 6, 8
Output through.

At the time of testing, by setting the test mode selection input terminal 2 to H', the signal input from the clock input terminal 1 is output as is through the NAND circuits 7 and 8.

In an integrated circuit that operates based on a signal obtained by dividing the clock input in this manner, it is common to have a test mode selection function to shorten the test time.

[Problem to be solved by the invention]

Conventional integrated circuit test circuits require a test mode selection input terminal to be provided on the integrated circuit in order to control the function of selecting an actual operating state and a test state.

The integrated circuit test circuit of the present invention is designed to eliminate the test mode selection input terminal, and is intended to reduce the number of terminals in the integrated circuit.

[Means to solve the problem]

In the integrated circuit test circuit of the present invention, the logic means is operated by a signal from a clock input terminal in order to control the function of selecting an actual operating state and a test state.

[Effect]

In the integrated circuit test circuit of the present invention, the function of selecting the fully operational state and the test state is controlled by the voltage level of the signal input to the clock input terminal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1(a), 1 is a clock input terminal, 3 is a clock input gate, 4 is a test mode selection gate,
5 is an inverter circuit, 6 to 8 are NAND circuits that constitute a data selection function, 11 to 12 are D-type flip-flops provided to select the actual operating state and test mode, and 21 to 2n are T circuits that constitute a division stage. It is a type of flip-flop.

Further, FIG. 1(b) is a time chart of input signals in the test state in the circuit of FIG. 1(a), and FIG.
1 is an input signal time chart in an actual operating state.

The test state is maintained by keeping the voltage level of the signal input to the clock input terminal 1 below the threshold value of the test mode selection gate 4.

On the other hand, in the actual operating state, since the voltage level of the signal input to the clock input terminal 1 exceeds the threshold of the test mode selection gate 4, the D-type flip-flops 11 and 12 operate and enter the test mode. The state will change from the state to the actual operating state.

As described above, by making the signal level applied to the clock input terminal 1 different in the test state from the actual operating state and by providing a function to judge the signal level, the test state and the actual operating state can be selected. Can be done.

〔Effect of the invention〕

As described above, according to the present invention, by making the signal levels of the clock input terminals different, it is possible to reduce the number of terminals of an integrated circuit having a clock input signal and a test mode function.

[Brief explanation of the drawing]

FIG. 1(a) is a circuit diagram of a test circuit for an integrated circuit according to an embodiment of the present invention; FIG. 1(a) is a time chart of input signals in the test state of FIG. ) is a time chart of input signals in the actual operating state of FIG. 1(a), and FIG. 2 is a circuit diagram of a conventional integrated circuit test circuit. In the figure, 1 is a clock input terminal, 3 is a clock input gate, 4 is a test mode selection gate, and kllN12 is a D-type flip-flop. Note that the same or equivalent parts are shown in the figures.

Claims (2)

[Claims] (1) A test circuit for an integrated circuit having a clock input terminal, characterized in that the integrated circuit has a function of selecting an actual operating state and a test operating state according to a signal level applied to the clock input terminal. (2) In an integrated circuit having a clock input terminal and a function of selecting an actual operating state and a test operating state, logic means is provided for setting the actual operating state or the test operating state in accordance with the signal level applied to the clock input terminal. An integrated circuit test circuit characterized by comprising: