JPH02108500U - - Google Patents
Info
- Publication number
- JPH02108500U JPH02108500U JP1576489U JP1576489U JPH02108500U JP H02108500 U JPH02108500 U JP H02108500U JP 1576489 U JP1576489 U JP 1576489U JP 1576489 U JP1576489 U JP 1576489U JP H02108500 U JPH02108500 U JP H02108500U
- Authority
- JP
- Japan
- Prior art keywords
- band
- signal
- bands
- channel
- signal level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
第1図はスペクトルアナライザ回路を利用して
構成した本考案の疑似ステレオ信号作成回路の1
実施例を示すブロツク図、第2図は同上実施例に
おける帯域周波数特性を示す図、第3図はグラフ
イツクイコライザ回路を利用して構成した本考案
の疑似ステレオ信号作成回路の1実施例を示すブ
ロツク図、第4図は同上実施例における帯域周波
数特性を示す図である。
1……スペクトルアナライザ回路、41〜44
……帯域フイルタ、11,12……加算器、31
L……Lチヤンネル用のイコライザ回路、31R
……Rチヤンネル用のイコライザ回路、331〜
335……帯域レベル調整回路、34……レベル
可変制御回路、35……周期調整つまみ、f1〜
f5……各帯域の中心周波数。
Figure 1 shows one of the pseudo stereo signal generation circuits of the present invention configured using a spectrum analyzer circuit.
FIG. 2 is a block diagram showing the embodiment; FIG. 2 is a diagram showing the band frequency characteristics of the same embodiment; FIG. 3 is an embodiment of the pseudo stereo signal generating circuit of the present invention constructed using a graphic equalizer circuit. The block diagram, FIG. 4, is a diagram showing band frequency characteristics in the same embodiment. 1...Spectrum analyzer circuit, 4 1 to 4 4
... Bandwidth filter, 11, 12 ... Adder, 31
L... Equalizer circuit for L channel, 31R
...Equalizer circuit for R channel, 33 1 ~
33 5 ...Band level adjustment circuit, 34...Level variable control circuit, 35...Period adjustment knob, f1 ~
f5 ... Center frequency of each band.
Claims (1)
数帯域に分割し、該分割した各帯域ごとにその信
号レベルを表示するようにしたスペクトルアナラ
イザ回路において、 前記複数の帯域中の所定の帯域の出力信号同士
を混合して一方のチヤンネルの疑似ステレオ信号
として出力する第1の信号加算手段と、 前記複数の帯域中の他の所定の帯域の出力信号
同士を混合して他方のチヤンネルの疑似ステレオ
信号として出力する第2の加算手段とを備えたこ
とを特徴とする疑似ステレオ信号作成回路。 (2) 左右チヤンネルのオーデイオ信号をそれぞ
れ所定の異なる複数の周波数帯域に分割し、該分
割した各帯域ごとにその信号レベルを調整して左
右チヤンネルの音質を調整するようにしたグラフ
イツクイコライザ回路において、 前記複数の帯域に分割された左右チヤンネルの
各帯域の信号レベルを自在に可変するレベル可変
制御手段を設け、 一方のチヤンネルの所定の帯域の信号レベルと
他の所定の帯域の信号レベルとを所定の周期で交
互に増減制御するとともに、該増減制御される各
帯域に対応する他方のチヤンネルの各帯域の出力
信号レベルを前記チヤンネルとは増減方向が逆と
なるように同一の周期で交互に増減制御するよう
にしたことを特徴とする疑似ステレオ信号作成回
路。[Claims for Utility Model Registration] (1) In a spectrum analyzer circuit that divides an audio signal into a plurality of predetermined different frequency bands and displays the signal level for each of the divided bands, a first signal adding means for mixing output signals of a predetermined band among the plurality of bands and outputting the mixture as a pseudo stereo signal of one channel; and mixing output signals of another predetermined band among the plurality of bands. 1. A pseudo-stereo signal generating circuit comprising: second addition means for outputting the pseudo-stereo signal of the other channel. (2) In a graphic equalizer circuit that divides the audio signals of the left and right channels into a plurality of predetermined different frequency bands, and adjusts the signal level for each divided band to adjust the sound quality of the left and right channels. , a level variable control means is provided for freely varying the signal level of each band of the left and right channels divided into the plurality of bands, and the signal level of a predetermined band of one channel and the signal level of the other predetermined band are adjusted. In addition to controlling the increase and decrease alternately at a predetermined period, the output signal level of each band of the other channel corresponding to each band to be increased and decreased is alternately controlled at the same period so that the direction of increase and decrease is opposite to that of the channel. A pseudo-stereo signal creation circuit characterized by increasing/decreasing control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1576489U JPH02108500U (en) | 1989-02-15 | 1989-02-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1576489U JPH02108500U (en) | 1989-02-15 | 1989-02-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02108500U true JPH02108500U (en) | 1990-08-29 |
Family
ID=31228101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1576489U Pending JPH02108500U (en) | 1989-02-15 | 1989-02-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02108500U (en) |
-
1989
- 1989-02-15 JP JP1576489U patent/JPH02108500U/ja active Pending
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