JPH02111841U - - Google Patents
Info
- Publication number
- JPH02111841U JPH02111841U JP1945789U JP1945789U JPH02111841U JP H02111841 U JPH02111841 U JP H02111841U JP 1945789 U JP1945789 U JP 1945789U JP 1945789 U JP1945789 U JP 1945789U JP H02111841 U JPH02111841 U JP H02111841U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- output signal
- logic circuit
- address bus
- gate interposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Description
第１図は本考案の第１の実施例のブロツク図で
ある。第２図は第１図に示された電子計算機装置
のアドレスの詳細を示す図表である。第３図は第
１図に示された電子計算機装置のメモリマツプを
示す図である。第４図は本考案の第２の実施例の
ブロツク図である。第５図は本考案の第３の実施
例のブロツク図である。第６図は第５図の動作を
説明するための図である。第７図は本考案の第４
の実施例のブロツク図である。
１…旧メモリ、２…高速メモリ、３…アドレス
バス、４…第１ゲート、４Ａ…制御端子、５…第
２ゲート、５Ａ…制御端子、６…アンドゲート、
１０９〜１１１…インバータ、Ｓ０９，Ｗ０９〜
Ｗ１１，Ｙ０９〜Ｙ１１…スイツチ。
FIG. 1 is a block diagram of a first embodiment of the present invention. FIG. 2 is a chart showing details of the addresses of the electronic computer device shown in FIG. FIG. 3 is a diagram showing a memory map of the electronic computer device shown in FIG. 1. FIG. 4 is a block diagram of a second embodiment of the present invention. FIG. 5 is a block diagram of a third embodiment of the present invention. FIG. 6 is a diagram for explaining the operation of FIG. 5. Figure 7 is the fourth part of this invention.
FIG. 2 is a block diagram of an embodiment of the invention. 1... old memory, 2... high speed memory, 3... address bus, 4... first gate, 4A... control terminal, 5... second gate, 5A... control terminal, 6... AND gate,
109-111...Inverter, S09, W09-
W11, Y09~Y11...Switch.
Claims (1)
１ゲートと、 前記第１メモリより高速な第２メモリ及びアド
レスバス間に介在された第２ゲートと、 アドレスバスに接続され、所定のアドレス領域
であるか否かに応じて出力信号を発生する論理回
路とを具備し、 前記論理回路の出力信号線は、前記第１及び第
２ゲートがそれぞれ逆に開閉されるように、それ
らの制御端子に接続されたことを特徴とする電子
計算機装置。[Claims for Utility Model Registration] A first gate interposed between a first memory and an address bus; a second gate interposed between a second memory faster than the first memory and the address bus; and a logic circuit that is connected to and generates an output signal depending on whether or not it is in a predetermined address area, and the output signal line of the logic circuit is such that the first and second gates are opened and closed in reverse, respectively. An electronic computer device characterized in that it is connected to the control terminals thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1945789U JPH02111841U (en) | 1989-02-21 | 1989-02-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1945789U JPH02111841U (en) | 1989-02-21 | 1989-02-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02111841U true JPH02111841U (en) | 1990-09-06 |
Family
ID=31234987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1945789U Pending JPH02111841U (en) | 1989-02-21 | 1989-02-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02111841U (en) |
-
1989
- 1989-02-21 JP JP1945789U patent/JPH02111841U/ja active Pending
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