JPH0211184B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction decoding method using a majority difference set cyclic code. More specifically, the present invention relates to an error correction decoding method for character code broadcasting in which digitally encoded character information is multiplexed transmitted during the vertical retrace period of a television signal and displayed on a home television receiver or the like. The present invention relates to an error correction decoding system that has significantly improved error correction capability compared to conventional decoding systems.

The decoding method using general majority difference set cyclic codes is a well-known technique, and is described, for example, in "Coding Theory" (published by Shokodo, by Miyagawa, Iwadare, and Imai, p.287-p.290). .

Traditionally, in Japanese character code broadcasting, it has been considered best to use the (272, 190) code as an error correction method. This is clear from Japanese Patent Application No. 58-6579 (Japanese Unexamined Patent Publication No. 59-133751) entitled ``Error Correction Decoding System'' filed by the present applicant.

Using the basic error correction decoding circuit proposed in the above-mentioned Japanese Patent Application No. 58-6579, it is possible to correct 8-bit errors in one packet (272 bits), but it is possible to correct errors of 9 bits or more. The problem was that it could hardly be corrected.

Another improved error correction decoding method proposed in the above-mentioned application (i.e., when errors cannot be corrected, errors of 9 bits or more can be corrected by shifting the first bit). method) had the disadvantage that the processing time was too long.

In view of the above-mentioned points, an object of the present invention is to provide an error correction decoding method that improves error correction capability and reduces processing time at the same time.

In order to achieve such an object, the present invention adds a subtraction circuit to the majority decision circuit in an error correction decoding system including a majority decision circuit, a syndrome register, and a data register using a majority decision set cyclic code, and also adds a subtraction circuit to the majority decision circuit. The determination threshold is set to a specific value within the number of input elements of the majority circuit, and after cyclic correction, a specific number is sequentially subtracted from the determination threshold via a subtraction circuit until the determination threshold reaches a predetermined value, and corrected decoding is performed. It is characterized by the following.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of an error correction decoding circuit to which the present invention is applied. In this figure, 100 is an output port, 101 is an input port, 102 is a parallel-to-serial/serial-to-parallel conversion circuit, 103 is a data register (272 stages), 1
04 is a timing generator, 105 is a load gate circuit, 106 is a syndrome register (82
stage), 107 is a majority circuit, 108 is a collect gate circuit, 109 is an error status register, 1
10 is a start signal, 111 is a load signal, 11
3 is a collect signal, 114 is data before error correction, 115 is data after error correction, 116 is serial load data, 117 is a ready signal, 118
119 is a syndrome register signal, 119 is an error correction signal, 120 is a load gate signal, 121 is a collect gate signal, 122 is a load timing signal, 123 is a loading clock signal, 124 is a clear signal, 126 is an error correction clock signal, 12
7 is an error status signal, 128 is an adder modulo 2, and 129 is a threshold designation signal (5 bits).

The basic circuit configuration of this embodiment is based on the previously mentioned patent application.
As described in No. 58-6579, the difference is that the threshold value can be changed by the threshold value designation signal 129, and that the component of the majority vote is made up of the first bit after being shortened by 1 bit. It's on. By orthogonalizing the data on the first bit of the transmitted data, the load end signal is no longer necessary.

Next, the operation of this embodiment will be explained. The feature of this embodiment is that the threshold values are set to 17, 16, 15,
The error correction ability is improved by correcting the numbers in the order of 14, 13, 12, 11, 10, and 9. This principle will be described later.

First, the CPU (not shown) specifies the threshold level (threshold specification signal 129) as 17 (5-bit information).
Next, the CPU issues a start command (start signal 11
0) and sets all 82 bits of the syndrome register 106 to “0” (reset signal 1
24). This prepares for the next load data. The CPU sequentially loads 272 bits of information for one packet, dividing it into 17 times of 16 bits each.
The CPU converts the load data into data 1 before error correction.
14 and generates a load command (see load signal 111).

Based on this load signal 111, a load gate signal 120 and a load clock signal (16 bits) 123 are generated, and the syndrome register 1
Load gate circuit 10 for guiding data to 06
5, data loading of the pre-error correction data 114 to the parallel-to-serial conversion circuit 102, 16-bit shift from the parallel-to-serial conversion circuit to the data register 103, 16-bit shift to the syndrome register 106, etc.

By repeating this operation 17 times, the first data reaches the leading edge of the data register 103. The syndrome register 106 has finished generating the syndrome. That is, the 82-bit syndrome register 106 represents the remainder when the data is divided by the generator polynomial G(2).

S(x)={a ₀ x ²⁷¹ +ax ²⁷⁰ +...+a ₂₇₀ x+a ₂₇₁ /g(x
)} Here, S(x) is the syndrome, a ₀ …a ₂₇₁ is
272-bit data, g(x) is from the aforementioned patent application 1982-
In the generator polynomial described in No. 6579, { } represents the remainder.

The error correction operation will now be explained. CPU
generates a collect signal 113 in response to a collect command. On the other hand, the timing generator 104
generates an error correction clock signal 126 for correcting, corrects errors only for 16 bits of data in the data register 103, and loads the corrected data into the serial-to-parallel conversion circuit 102. This error correction is performed using an exclusive OR circuit (2
(modulo adder) 108. The error correction signal 119 is a linear combination of 17 states of the 82 syndrome registers, which will be described later. Among the 17 states, the majority circuit 107 determines a threshold (the first threshold is
17: This is output by comparing with the threshold value designation signal 129).

However, this error correction signal 119 is configured to pass only during an error correction operation in response to a collect gate signal (see collect gate circuit 108). Further, as in the case of error correction operation, the error correction signal 119 modifies the syndrome register 106 when there is an error in that bit so as to remove the influence of that bit.

After performing 16-bit error correction on the collect signal 113 in this manner, the CPU confirms that the ready signal 117 is generated and reads the data 115 from the input port 101. Then, the collect signal 113 is output 17 times to restore the signal for one packet of 272 bits. At this time, by checking the error status signal 127, it can be determined whether or not error correction has been performed correctly. Furthermore, if the syndrome register 106 is not all "0", it means that an error still exists in one of the bit positions, so the error correction operation is performed again. However, in this case, the threshold value of the majority circuit is decreased by 1. That is, the threshold value is set to 16, and data after error correction is performed using the previous threshold value of 17 is used.

The above operations are performed until the threshold value 9 is completed. However, when the syndrome register 106 becomes all "0" during the process, it means that the error correction operation is completed. That is, since the data at that point has a correct value, there is no need to pass it through the error correction circuit from then on. In this embodiment, the data on the input/output port is handled as 16 bits, but the same applies to other numbers of bits.

FIG. 2 is a flowchart showing the control procedure of FIG. 1. Here, in order to simplify the circuit, a composite check matrix is used that is not orthogonal on the shortened bits, but is orthogonal on the first bit of the actual transmission bits. This eliminates the need for the syndrome register to be idled by the load end command signal, as disclosed in the aforementioned Japanese Patent Application No. 58-6579. In other words, the load end signal is no longer necessary.

The contents of the syndrome register 106 are S ₀ ,
S ₁ ,...S ₈₀ , S ₈₁ are composite check matrices A ₀ , A ₁ ,..., A ₁₆ that are orthogonal on the first transmission bit.
is as follows.

A ₀ = S ₁₆ A ₁ = S ₇₀ + S ₇₅ A ₂ = S ₄ + S ₂₂ A ₃ = S ₂₀ + S ₂₆ + S ₄₄ A ₄ = S ₂ + S ₂₄ + S ₃₀ + S ₄₈ A ₅ = S ₃₄ + S ₅₁ + S ₅₆ + S ₇₇ A ₆ = S ₇ + S ₄₃ + S ₆₀ + S ₆₄ A ₇ = S ₁₅ + _S19 + S ₄₁ + S ₄₇ + S ₆₅ A 8 = S 65 A ₈ = S _{65 S 63 +} S ₆₇ A ₉ = S ₆₇ A ₉ = S ₄₉ + S ₃₁ + S ₄₅ + S ₄₅₄ + S ₄₅₄ A ₁₀ =S ₉ +S ₁₂ +S ₂₁ +S ₅₇ +S ₇₄ +S ₇₈ A ₁₁ =S ₅ +S ₃₆ +S ₃₈ +S ₄₉ +S ₅₂ +S ₆₁ A ₁₂ =S ₆ +S ₃₇ +S ₃₈ +S ₅₀ +S ₅₃ +S ₆₂ A ₁₃ =S ₀ +S ₁₁ +S ₁₄ +S ₂₃ +S ₅₉ +S ₇₆ +S ₈₀ A ₁₄ =S ₈ +S ₂₇ +S ₂₈ +S ₃₅ +S ₆₆ +S ₆₈ +S ₇₉ A ₁₅ =S ₃ +S ₁₃ +S ₃₂ +S ₃₃ +S ₄₀ +S ₇₁ +S ₇₃ A ₁₆ =S ₁₇ +S ₁₈ +S ₂₅ +S ₅₆ +S ₅₈ +S ₆₉ +S ₇₂ +S ₈₁ Next, set the threshold of the majority circuit to 17, 16, 15, ..., 9
We will explain the advantage of sequentially lowering the value starting from a high value. Now, as an example, consider a case where the threshold value is 17. In this case, when the number of errors is 16 or less, no erroneous correction is performed (with a threshold of 9, erroneous correction may be performed). The composite check matrix A when the shortening bit is omitted has the following form.

If there are 16 or less errors in locations other than the leading bit, the number of "1"s in the product of the error pattern and matrix A is "16" at most. Since the threshold value is 17, no error correction is performed. That is,
Mistakes will not be corrected. Additionally, if 16 or fewer errors occur in a location that includes the first bit,
The number of "1"s in the product of the error pattern and matrix A may be 17. Naturally, if it is only the first bit, it will be 17. Even if 15 errors are concentrated only in each row of A that includes the first bit, the number of "1"s will be 17. In such a case, since the first bit is corrected, only the first bit will be correctly corrected. Since the above-mentioned operation is repeated 272 times, by setting the threshold to 17, some of the errors of 16 or less will be corrected. What's more, they will not make any false corrections.

Next, if the threshold value is lowered to 16 and the same operation as described above is performed, erroneous corrections will not be made for 15 or fewer errors, but some correct error corrections will be made.

Furthermore, error correction is performed by setting thresholds to 15, 14, 13, 12, 11, and 10. This will correct significant errors of less than 16 bits to less than 9 bits.

Finally, the original threshold value 9 is set to perform error correction. In this case, all remaining errors of 8 bits or less can be corrected by the inherent code error correction ability.

As described above, by lowering the threshold value to 17 to 9 and sequentially performing error correction, it is possible to correct all errors of 8 bits or less and most of the errors of 9 bits to 16 bits.

FIG. 3 shows a second embodiment to which the present invention is applied. FIG. 4 is a flowchart showing the control procedure of the CPU (not shown).

The error correction circuit shown in FIG. 1 is of a type that resets the threshold each time, reloads the data obtained by the previous error correction, and then performs the correction. Therefore, a considerable amount of processing time is required. The error correction circuit shown in FIG. 3 is mostly implemented in hardware to enable high-speed processing. The circuit configuration is almost the same as that in FIG. 1, except that error correction processing and threshold setting are automatically performed. Note that components having substantially the same functions as those shown in FIG. 1 are given the same numbers.

In this figure, 300 is a data selector, 301 is a timing generator, 302 is a majority circuit, 3
03 is a data read signal, 304 is a dummy clock signal, 305 is a data load clock signal, 3
06 is a collect clock signal, 307 is storage data to be used next time, 308 is serial data after error correction, and 309 is a timing signal at the time when one packet of data has been tested.

As mentioned in Figure 1, the CPU (not shown)
generates a start signal 110. In response to this start signal, the timing generator 301
generates a reset signal 124, clears all registers in the syndrome register 106, and sets the threshold of the majority circuit 302 to 17. Next, the CPU processes the data 114 before error correction.
Set parallel data as load signal 1
11 to load the data. The load to the parallel-to-serial conversion circuit 102 is the load clock signal 1.
This is done using 22. After this parallel load,
Data is loaded into data register 103 and syndrome register 106 in response to load clock signal 123. Data selector 30
0 is a gate circuit for passing load data during loading and for passing storage data 307 during error correction. In this way, loading of all 272 bits of data for one packet is completed.

When data loading is completed, timing generator 301 outputs a signal for error correction operation. That is, the collect gate circuit 108 is opened, and the syndrome register 106 is incremented, the data register 103 is incremented, and error correction is performed by the collect clock signal 306. The threshold used initially is 17. This error correction operation is performed in the first
As described in the figure, all 272 bits are processed. At this time, 272 bits of error-corrected data remain in the data register 103 after processing with the threshold value of 17.

At this stage, the error status signal 12
7 indicates an error, data register 1
This means that errors still remain in the data in 03. Therefore, in this case, the threshold value is decreased by 1 and error correction is performed again.

The majority circuit 302 outputs the error status signal 12
7 and when it is determined that an error still exists, the threshold value is decreased by 1 in response to the timing of the 1 packet end signal. Since the period of the syndrome register 106 is 273 bits, the period of the syndrome register 106 is 273 bits.
06 by 1 bit. After that, error correction is performed using a threshold value of 16.

Once all errors have been corrected and the error status signal 127 indicates so, the CPU enters the data read.

If the error cannot be corrected even if the threshold value is lowered to 9, an error is displayed on the error status signal 127 and a ready signal 117 is output.

To read data, data read signal 303
done in response to. Data read clock signal 30
5 leads the data in the data register 103 to the serial-to-parallel conversion circuit 102. In response to the ready signal 117, the CPU repeatedly outputs a data read signal 303 for reading the parallel data 115, thereby restoring one packet of data after error correction.

FIG. 5 is a block diagram illustrating the operation of the majority circuit. Here, 500 is a majority input signal (A ₀ to A ₁₆ ), 501 is a majority circuit, 502 is a subtraction circuit, 503 is a gate circuit, 504 is a subtraction command signal for subtracting the threshold by 1, 505 is a threshold signal, and 506 is the majority vote output signal. Further, as mentioned above, 108 is a collect gate circuit, 124 is a clear signal, 127 is an error status signal, 3
09 is a 1 packet end signal.

The subtraction circuit 502 is previously set to "17" by the reset signal 124. i.e. 17
is the first threshold. When the first bit-by-bit correction of 272 bits is completed, the 1-packet end signal 309 controls the gate 503 to pass the error status signal 127, and then sends out the subtraction command signal 504. In response to this subtraction command signal 504, the initially set threshold value 17 is subtracted by 1 and set to 16, and a threshold value signal 505 is sent out. In the majority decision circuit 501, the majority decision input signal A ₀
~ _A16 , the majority vote output signal 506 is output only when the value is greater than the threshold specified by the threshold signal 505. This is done for each bit, and the operation at threshold 16 is completed.

Furthermore, the above-described operation is repeated for threshold values 15 to 9.

In each of the embodiments shown in FIG. 1 and FIG. 3, error correction was performed by lowering the threshold value in the order of 17, ..., 9, but for example, if the threshold value in the middle was lowered to 11, 10, etc.
By setting as in 9, the processing time can be shortened. In this case, the error correction ability will be slightly lower than in the above embodiment.
That is, in this case, all errors of 8 bits or less and a significant number of 9-bit and 10-bit errors will be corrected. In addition, the threshold value can be set as, for example,
17, 15, 13, 11, and 9, the error correction operation can be similarly completed in a short time.

It goes without saying that by fixing the threshold value to 9 and performing the correction operation multiple times, it is possible to increase the probability of correcting errors that could not be corrected in the previous error correction operation.

As explained above, according to the present invention, all errors of 8 bits or less in one packet can be corrected, and errors of 9 bits or more and 16 bits or less can be corrected at a considerable rate. It is possible to enlarge the image and reduce erroneous display. According to computer simulation, 9 bits and 10 bits are 100%, 11
BIT was able to correct errors of about 95%.

In addition, in the first embodiment shown in Fig. 1, only the threshold value can be specified from the outside without changing the basic error correction circuit, so a software section is added to the conventional circuit. This has the advantage that it can be easily realized by doing so.

Furthermore, in the second embodiment shown in FIG. 3, the software section of the first embodiment described above is implemented by hardware, so high-speed processing is possible.

In the third embodiment mentioned last, the number of types of threshold values to be sequentially lowered is reduced, so the time required for error correction can be shortened.

As described above, the present invention can be applied to character code broadcasting that uses the vertical retrace period of a television signal, but it can also be applied to code broadcasting using a dedicated waveform that uses all television lines for transmission. It is. Furthermore, it can be applied to other majority code decoding circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a flowchart showing the control procedure of FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, FIG. 4 is a flowchart showing the control means of FIG. 3, and FIG. 5 is a majority decision. FIG. 3 is an explanatory diagram of the operation of the circuit. 100...Output port, 101...Input port, 102...Parallel/serial/parallel conversion circuit, 103...
Data register, 104... Timing generator, 105... Load gate circuit, 106...
Syndrome register, 107...majority circuit,
108...Collect gate circuit, 109...Error status register, 110...Start signal, 111...Load signal, 113...Collect signal, 114...Data before error correction, 115...
... Data after error correction, 116 ... Serial load data, 117 ... Ready signal, 118 ... Syndrome register signal, 119 ... Error correction signal, 120 ... Load gate signal, 121 ... Collect gate signal, 122 ... ...Load timing signal, 123...Load clock signal, 124
...Reset signal, 126...Error correction clock signal, 127...Error status signal, 128
... Adder modulo 2, 129 ... Threshold specification signal, 300 ... Data selector, 301 ... Timing generator, 302 ... Majority circuit, 3
03...Data read signal, 304...Dummy clock signal, 305...Data read clock signal, 306...Collect clock signal, 307...
... Data for storage, 308 ... Serial data after error correction, 309 ... 1 packet end signal, 5
00...Majority input signal, 501...Majority circuit, 502...Subtraction circuit, 503...Gate circuit, 504...-1 command signal, 505...Threshold signal, 506...Majority output signal.

Claims (1)

[Scope of Claims] 1. In an error correction decoding system including a majority decision circuit, a syndrome register, and a data register using a majority decision set cyclic code, a subtraction circuit is added to the majority decision circuit, and a decision threshold of the majority decision circuit is added. is set to a specific value within the number of input elements of the majority circuit, and after cyclic correction, the subtraction circuit sequentially subtracts a specific number from the judgment threshold until the judgment threshold reaches a predetermined value to perform corrected decoding. An error correction decoding method characterized by: 2 Using a data signal of 272 bits, an information signal of 190 bits, and a parity bit of 82 bits, the judgment threshold of the majority decision circuit is set to 17 in advance, and the specified number is set to 1, and the judgment threshold 17 is sequentially reduced to half the value of 9. Claim 1 characterized in that the correction decoding is performed by reducing the amount until the
Error correction decoding method described in section. 3. The error correction decoding system according to claim 1, wherein the setting of the determination threshold value is changed based on a command from an external device. 4. The error according to claim 1, characterized in that the determination threshold value setting and the data reloading operation are performed by hardware, thereby shortening the error processing time and reducing the burden on the software. Correction decoding method. 5. The error correction decoding system according to claim 1, wherein the amount of decrease of the determination threshold value is set to 2 or 3 to shorten the error correction time. 6. The error correction decoding system according to claim 1, wherein the determination threshold is started from 17 or less to shorten error correction time.