JPH02113484U - - Google Patents
Info
- Publication number
- JPH02113484U JPH02113484U JP2264789U JP2264789U JPH02113484U JP H02113484 U JPH02113484 U JP H02113484U JP 2264789 U JP2264789 U JP 2264789U JP 2264789 U JP2264789 U JP 2264789U JP H02113484 U JPH02113484 U JP H02113484U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- memory
- stored
- processing device
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案によるビデオ信号処理装置の一
実施例を示す構成図、第２図は従来のビデオ信号
処理装置例を示す構成図、第３図はＡ／Ｄ変換器
による階調分けの対象となるビデオ信号の白・黒
レベル間変動例を示す説明図である。
１０は原色信号ＲのメモリブロツクであるＲブ
ロツク、１１はＡ／Ｄ変換器、１２はＤ／Ａ変換
器、１４はフレームメモリ、１６，１７はラツチ
回路、１５，１８は信号を切り替えるセレクタ、
２０は原色信号ＧのメモリブロツクであるＧブロ
ツク、３０は原色信号Ｂのメモリブロツクである
Ｂブロツクである。
Fig. 1 is a block diagram showing an example of a video signal processing device according to the present invention, Fig. 2 is a block diagram showing an example of a conventional video signal processing device, and Fig. 3 is a block diagram showing an example of a conventional video signal processing device. FIG. 3 is an explanatory diagram showing an example of variation between white and black levels of a target video signal. 10 is an R block which is a memory block for the primary color signal R; 11 is an A/D converter; 12 is a D/A converter; 14 is a frame memory; 16 and 17 are latch circuits; 15 and 18 are selectors for switching signals;
20 is a G block which is a memory block for the primary color signal G, and 30 is a B block which is a memory block for the primary color signal B.
Claims (1)
るスルー画と、Ａ／Ｄ変換器を介してメモリに記
憶した後のビデオ信号から形成されるメモリ画と
を形成するためのビデオ信号処理装置において、 上記Ａ／Ｄ変換器からメモリへ書込むビデオ信
号を分岐して、この分岐ビデオ信号とメモリから
読み出したビデオ信号とを入力とするラツチ回路
を設けて、これにより分岐ビデオ信号とメモリ読
出しビデオ信号との同期を取り、 これら同期を取つた信号をＤ／Ａ変換して、メ
モリに記憶する前のスルー画ビデオ信号と、メモ
リに記憶させた後のメモリ画ビデオ信号とを形成
し、 上記スルー画ビデオ信号とメモリ画ビデオ信号
とを切替え自在に出力するように構成したことを
特徴とするビデオ信号処理装置。[Claims for Utility Model Registration] A through image formed from a video signal before being stored in a memory, and a memory image formed from a video signal after being stored in a memory via an A/D converter. In the video signal processing device for the purpose of The branch video signal and the memory read video signal are synchronized, and these synchronized signals are D/A converted to produce a live image video signal before being stored in the memory and a memory image video after being stored in the memory. What is claimed is: 1. A video signal processing device comprising: a video signal processing device configured to output a live image video signal and a memory image video signal in a switchable manner;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264789U JPH02113484U (en) | 1989-02-28 | 1989-02-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264789U JPH02113484U (en) | 1989-02-28 | 1989-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02113484U true JPH02113484U (en) | 1990-09-11 |
Family
ID=31240947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2264789U Pending JPH02113484U (en) | 1989-02-28 | 1989-02-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02113484U (en) |
-
1989
- 1989-02-28 JP JP2264789U patent/JPH02113484U/ja active Pending
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