JPH02114538A - High frequency high power field effect transistor - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a high frequency, high power field effect transistor, and particularly to the structure of a field effect transistor having a vertical MO3 structure.

[Conventional technology]

Conventionally, this type of high-power MO8FET has been widely used with a vertical MO8 structure, which has the advantage that the on-resistance does not increase significantly even when designed with a high breakdown voltage, and the gate width per unit chip area can be increased. This structure is the second
As shown in the figure, a drain region 2 of the same conductivity type is provided on a highly impurity-concentrated substrate 6, and this drain region 2 includes a back gate region 1 of an opposite conductivity type and a source region 5 of the same conductivity type as the substrate 6.
A gate electrode 4 is provided between a source region 5 and a drain region 2 with a gate oxide film 7 interposed therebetween, and a source electrode 9 is provided between the source region 5 and the drain region 2.
is connected to the source region 5 and the back gate region l. In order to achieve high frequency using such a vertical MO3 structure, as shown in FIG. 2, the back gate 1 and source region 5 are formed by diffusion or ion implantation in self-alignment with the gate electrode 4. A common method has been to reduce the overlap capacitance between the source region 5 and the gate electrode 4. At this time, since the drain region 2 is not formed in self-alignment with the gate electrode 4, the diffusion time of the back gate region 1 is controlled so that the back gate region l does not protrude from the gate electrode 4 toward the drain region 2 as much as possible. Ta. An example using this kind of structure is, for example, IE
DM 84-447~450”A 900MHz 1
00W VD-MOSFET WITH5ILICID
E GATE 5ELF-ALIGNED CANNE
It is shown in "L".

[Problem to be solved by the invention]

In the structure of the conventional vertical MO8FET described above, the back gate region 1 extends only to about 0.5 μm inside the gate electrode 4 in consideration of diffusion variations.
A certain amount of feedback capacitance between the gate and the drain must be assumed as a design value, which causes a decrease in the gain-bandwidth product. In addition, in the case of high-output transistors, the chip area becomes large, so variations in the channel length and feedback capacitance of the unit transistor are caused by both variations in the diffusion length of the back gate region 1 and variations in the length of the gate electrode 4. This has the disadvantage that the synthesis loss increases.

[Means to solve the problem]

According to the present invention, the high-frequency, high-output electric field effect of the vertical structure has a back gate region that protrudes from the gate electrode to the drain region, and an intrinsic drain region that has the same impurity concentration as the drain region on the surface of the protruded back gate region. Get a transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a structural cross-sectional view of a vertical MO3FET according to an embodiment of the present invention. Back gate region 1 and source region 5 are formed in self-alignment with gate electrode 4 . Furthermore, the back gate region 1 protrudes from the gate electrode 4 toward the drain region 2 side when viewed from the source region 5, and the surface of this protruding back gate region 1 has a surface that is self-aligned with the gate electrode 4. , has an intrinsic drain region 3 having an impurity concentration comparable to that of the drain region 2. Here, the reason why the impurity concentration of the intrinsic drain region 3 is made to be approximately the same as that of the drain region 2 is to prevent the breakdown voltage from deteriorating due to the intrinsic drain portion. By adopting the above structure, the channel length is determined only by the gate electrode 4, and the channel length is determined only by the gate electrode 4. Since the feedback capacitance between the drain regions 2 is also determined by the lateral extent of the intrinsic drain region 3, an FET with little variation and excellent high frequency characteristics can be manufactured.

Next, the effects of the above embodiment will be shown using numerical examples. In the case of a vertical structure, since the channel portion is formed by diffusion, the channel length is usually designed to be 3 μm or less.

In the case of the conventional structure shown in FIG. 2, the channel length is 2.
When designing with a target of 5 μm, gate width of 20 cm, and breakdown voltage of 100 V or more, the gain-bandwidth product results as shown below. At this time, the overlap between the gate and the drain must be approximately 1.5 μm, since it is necessary to take into account variations in diffusion and variations in gate electrode length conversion difference. The gain-bandwidth product (fT) is expressed as: 1:'τ2); Under the above conditions, c, , = 300 pF.

g,,=2. c, d=l OOpF, R,=lΩ, and the gain bandwidth product f1 is 300 MHz.

On the other hand, if the structure of the embodiment shown in FIG. 1 is constructed with the same dimension, the overlap between the gate and drain will be 0.3
Since it is reduced to approximately μm, C, d becomes 21 pF, and the gain bandwidth product fT increases to approximately 470 MHz.

The material for the gate electrode 4 may be any material that can serve as a mask when forming the source region 5 or the intrinsic drain region 3 and that can withstand high-temperature heat treatment when forming the back gate region 1. There are no particular restrictions. Usually, polysilicon, molybdenum, tungsten, or a compound of the above materials is used.

〔Effect of the invention〕

As explained above, the present invention provides a vertical MO8FET with a structure in which the back gate region protrudes from the gate electrode toward the drain region when viewed from the source region, and the surface of the drain region from the gate electrode has the same extent as the drain region. By forming the intrinsic drain region in self-alignment with the gate electrode, the channel length can be controlled only by the gate electrode length, and feedback capacitance can be reduced, reducing combined loss and widening the gain bandwidth product. It has the effect of being removed.

5...Source region, 6...High impurity concentration substrate, 7...Gate oxide film, 8...
Interlayer insulating film, 9...source electrode.

Claims (1)

[Claims] A semiconductor layer of a first conductivity type and a low impurity concentration is provided on a semiconductor substrate of a first conductivity type and a high impurity concentration, the semiconductor layer of the low impurity concentration is used as a drain region, and the surface side of the semiconductor layer of the low impurity concentration is provided. In a field effect transistor having a vertical structure in which a back gate region and a source region are formed, the back gate region has a structure in which the back gate region protrudes from the gate electrode toward the drain region side when viewed from the source region, and A high frequency device characterized in that an intrinsic drain region having an impurity concentration similar to that of the low impurity concentration region is formed on the surface of the back gate region protruding from the electrode toward the drain region in a self-aligned manner with respect to the gate electrode. High power field effect transistor.