JPH0211504U - - Google Patents

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Publication number
JPH0211504U
JPH0211504U JP8620488U JP8620488U JPH0211504U JP H0211504 U JPH0211504 U JP H0211504U JP 8620488 U JP8620488 U JP 8620488U JP 8620488 U JP8620488 U JP 8620488U JP H0211504 U JPH0211504 U JP H0211504U
Authority
JP
Japan
Prior art keywords
mute
signal
section
switching pulse
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8620488U
Other languages
Japanese (ja)
Other versions
JP2526794Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988086204U priority Critical patent/JP2526794Y2/en
Publication of JPH0211504U publication Critical patent/JPH0211504U/ja
Application granted granted Critical
Publication of JP2526794Y2 publication Critical patent/JP2526794Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Digital Magnetic Recording (AREA)
  • Recording Or Reproducing By Magnetic Means (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の1つの実施例に係るDAT
の構成を示すブロツク図、第2図は第1図のDフ
リツプフロツプの動作を説明するタイムチヤート
、第3図は他の実施例に掛かるDATの構成を示
すブロツク図、第4図は第3図中のマイクロコン
ピユータの動作を示すフローチヤート、第5図は
第4図の動作を説明するタイムチヤートである。 10,10A:信号処理回路、12,12A:
マイクロコンピユータ、16:ミユートスイツチ
、24:スイツチングパルス発生器、26:Dフ
リツプフロツプ、30:カウンタ回路。
Figure 1 shows a DAT according to one embodiment of this invention.
2 is a time chart explaining the operation of the D flip-flop shown in FIG. 1, FIG. 3 is a block diagram showing the structure of a DAT according to another embodiment, and FIG. 4 is a time chart showing the operation of the D flip-flop shown in FIG. FIG. 5 is a flowchart showing the operation of the microcomputer therein, and FIG. 5 is a time chart explaining the operation of FIG. 10, 10A: signal processing circuit, 12, 12A:
Microcomputer, 16: Mute switch, 24: Switching pulse generator, 26: D flip-flop, 30: Counter circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) ミユートオン・オフ信号に従いオーデイオ
信号に対するミユートを行うミユート部と、回転
シリンダの回転に応じたスイツチングパルスを発
生するスイツチングパルス発生部と、を有するD
ATにおいて、 ミユート部のミユートオン・オフ信号の入力側
に、同期化部を設け、 この同期化部は、外部からミユートオン・オフ
信号を入力すると、その後スイツチングパルス発
生部が発生したスイツチングパルスに同期させて
ミユートオン・オフ信号をミユート部へ出力する
こと、 を特徴とするDAT。 (2) ミユートオン・オフ信号に従いオーデイオ
信号に対するミユートのオン・オフを行うミユー
ト部と、回転シリンダの回転に応じたスイツチン
グパルスを発生するスイツチングパルス発生部と
を有するDATにおいて、 外部からミユートオン信号を入力するとその後
スイツチングパルス発生部が発生したスイツチン
グパルスに同期させてミユートオン信号をミユー
ト部へ出力するミユートオン同期化部と、 外部からミユートオン信号を入力するとその後
スイツチングパルス発生部が発生したスイツチン
グパルスを計数する計数部と、 この計数部が所定の設定値だけ計数したときの
スイツチングパルスに同期させてミユートオフ信
号をミユート部へ出力するミユートオフ信号発生
部と、 を備えたことを特徴とするDAT。 (3) ミユートオフ信号発生部の設定値は可変で
きることを特徴とする第2項記載のDAT。
[Claims for Utility Model Registration] (1) A D having a mute section that mutes an audio signal in accordance with a mute on/off signal, and a switching pulse generator that generates a switching pulse according to the rotation of a rotary cylinder.
In the AT, a synchronization section is provided on the input side of the mute on/off signal of the mute section, and when the mute on/off signal is inputted from the outside, this synchronization section synchronizes with the switching pulse generated by the switching pulse generator. A DAT characterized by outputting mute on/off signals to a mute section in synchronization. (2) In a DAT that has a mute section that turns on and off the mute in response to an audio signal according to the mute on/off signal, and a switching pulse generator that generates a switching pulse according to the rotation of the rotating cylinder, the mute on signal is received from the outside. When inputted, the mute-on synchronization part synchronizes with the switching pulse generated by the switching pulse generator and outputs the mute-on signal to the mute part, and when the mute-on signal is inputted from the outside, the switch generated by the switching pulse generator then outputs the mute-on signal to the mute part. a counting section that counts switching pulses; and a mute-off signal generating section that outputs a mute-off signal to the mute section in synchronization with a switching pulse when the counting section counts a predetermined set value. DAT to do. (3) The DAT according to item 2, wherein the set value of the mute-off signal generator is variable.
JP1988086204U 1988-06-29 1988-06-29 Magnetic tape recording / reproducing device Expired - Lifetime JP2526794Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988086204U JP2526794Y2 (en) 1988-06-29 1988-06-29 Magnetic tape recording / reproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988086204U JP2526794Y2 (en) 1988-06-29 1988-06-29 Magnetic tape recording / reproducing device

Publications (2)

Publication Number Publication Date
JPH0211504U true JPH0211504U (en) 1990-01-24
JP2526794Y2 JP2526794Y2 (en) 1997-02-19

Family

ID=31310847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988086204U Expired - Lifetime JP2526794Y2 (en) 1988-06-29 1988-06-29 Magnetic tape recording / reproducing device

Country Status (1)

Country Link
JP (1) JP2526794Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59126388A (en) * 1982-07-21 1984-07-20 Toshiba Corp Method and apparatus of consecutive recording for video tape recorder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59126388A (en) * 1982-07-21 1984-07-20 Toshiba Corp Method and apparatus of consecutive recording for video tape recorder

Also Published As

Publication number Publication date
JP2526794Y2 (en) 1997-02-19

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