JPH02117592U - - Google Patents
Info
- Publication number
- JPH02117592U JPH02117592U JP2547589U JP2547589U JPH02117592U JP H02117592 U JPH02117592 U JP H02117592U JP 2547589 U JP2547589 U JP 2547589U JP 2547589 U JP2547589 U JP 2547589U JP H02117592 U JPH02117592 U JP H02117592U
- Authority
- JP
- Japan
- Prior art keywords
- register
- data
- adder
- stores
- enlarging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010354 integration Effects 0.000 claims 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Image Processing (AREA)
Description
図は本考案を実施した任意倍率拡大装置の構成
ブロツク図である。
1……描画プロセツサ、2……フレーム・バツ
フア、3……ソース・データ・レジスタ、4……
デステイネーシヨン・データ・レジスタ、5……
拡大率レジスタ、6……加算器、7……積算レジ
スタ、DB……データ・バス。
The figure is a block diagram of an arbitrary magnification enlarging device embodying the present invention. 1...Drawing processor, 2...Frame buffer, 3...Source data register, 4...
Destination data register, 5...
Enlargement ratio register, 6...adder, 7...accumulation register, DB...data bus.
Claims (1)
タと、この描画データに拡大処理を施した結果を
格納するデステイネーシヨン・データ・レジスタ
と、拡大倍率の逆数値が設定される拡大率レジス
タと、前記デステイネーシヨン・データ・レジス
タに対する書き込みタイミングで前記逆数値を加
算する加算器と、この加算器の加算値を逐次格納
して前記加算器に戻す積算レジスタとを有し、前
記デステイネーシヨン・データ・レジスタは書き
込みタイミングで前記ソース・データ・レジスタ
からのデータを取り込み、前記ソース・データ・
レジスタは前記加算器からキヤリー出力がなされ
たタイミングで内部の描画データをシフトするこ
とを特徴とする任意倍率拡大装置。 A source data register that stores drawing data, a destination data register that stores the result of enlarging the drawing data, an enlargement ratio register in which the inverse value of the enlargement ratio is set, and the destination data register that stores the result of enlarging the drawing data. It has an adder that adds the reciprocal value at the writing timing to the destination data register, and an integration register that sequentially stores the added value of this adder and returns it to the adder. The register takes in data from the source data register at write timing, and writes the data to the source data register.
An arbitrary magnification enlarging device characterized in that the register shifts internal drawing data at the timing when a carry output is made from the adder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2547589U JPH02117592U (en) | 1989-03-06 | 1989-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2547589U JPH02117592U (en) | 1989-03-06 | 1989-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02117592U true JPH02117592U (en) | 1990-09-20 |
Family
ID=31246246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2547589U Pending JPH02117592U (en) | 1989-03-06 | 1989-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02117592U (en) |
-
1989
- 1989-03-06 JP JP2547589U patent/JPH02117592U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6034648U (en) | Memory paging system in microcomputer | |
| JPH02117592U (en) | ||
| JPS58147382U (en) | headphone | |
| JPS6348246U (en) | ||
| JPH0218161U (en) | ||
| JPS6013064U (en) | mirror device | |
| JPH0223751U (en) | ||
| JPS5881654U (en) | arithmetic processing unit | |
| JPS6452076U (en) | ||
| JPS6327952U (en) | ||
| JPS58155050U (en) | electronic register | |
| JPS59181490U (en) | CRT plotting device | |
| JPS6181333U (en) | ||
| JPS6056098U (en) | Reverberation adding device with analog mixer circuit | |
| JPS63173289U (en) | ||
| JPS62121652U (en) | ||
| JPS60107896U (en) | Display memory control circuit | |
| JPH0420139U (en) | ||
| JPS60150687U (en) | Magnetic tape control device | |
| JPH0412023U (en) | ||
| JPS5966291U (en) | electronic musical instruments | |
| JPS5836455U (en) | Kanji output device | |
| JPS59188531U (en) | Flap gate device | |
| JPS59166571U (en) | Binary figure data scaling circuit | |
| JPS63179548U (en) |