JPH02121475A - video signal processing equipment - Google Patents
video signal processing equipmentInfo
- Publication number
- JPH02121475A JPH02121475A JP27335688A JP27335688A JPH02121475A JP H02121475 A JPH02121475 A JP H02121475A JP 27335688 A JP27335688 A JP 27335688A JP 27335688 A JP27335688 A JP 27335688A JP H02121475 A JPH02121475 A JP H02121475A
- Authority
- JP
- Japan
- Prior art keywords
- digital video
- video signal
- signal
- field memory
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Studio Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、フィールドメモリを用いたビデオイ、３号処
理装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a video processing device using a field memory.
（従来の技術）
従来、デジタル特殊効果は、ビデオ信号をデジタル化し
１１フイールドメモリに蓄え、そのメモリ内容を１し
出力するデシタル１１１号処理てあって、スチルなとの
特殊内ノ１をノイズレスて行ったり、５ＩＩＩ１１面表
示とかワイプやフェート等の機能に利用される。あるい
はノイズリデューサ（！１１ ＋’（軽減装置）の様に
フィールド間にわたり、ｆｌｓ号６１１算を行うフィー
ルド間デジタルイ、−：号処理がある。 般に使われて
いる、１枚のフィールドメモリで繰退し加ｔ）の出来る
巡同形ノイズリデューサを利用したブロック図を第２図
に示す。(Prior art) Conventionally, digital special effects have been processed using digital No. 111 processing, which digitizes the video signal, stores it in 11 field memory, and outputs the memory contents by 1. It is used for functions such as 5III 11-screen display, wipe, and fade. Alternatively, there is inter-field digital I, -: signal processing that performs FLS signal 611 calculations between fields, such as a noise reducer (!11 +' (reduction device). FIG. 2 shows a block diagram using a cyclic noise reducer capable of repeating addition t).
このブロックを部用に説明すると、カメラ２からのビデ
オ４．１号をＡＤ変換器３でアナログからデジタルに一
＆換し、この入力デジタルビデオ信号は処理回路１４の
乗算部１２で（１−Ｋ）倍に減衰され加算部１３を経て
フィールドメモリ６に入り、次に乗算部１１でに４？、
され、加算部１３に入力され、ループ巡回する。To explain this block in detail, the video 4.1 from the camera 2 is converted from analog to digital by the AD converter 3, and this input digital video signal is converted by the multiplier 12 of the processing circuit 14 to (1- K) It is attenuated twice and enters the field memory 6 via the adder 13, and then goes to the multiplier 11 to become 4? ,
is input to the adder 13, and circulates in a loop.
Ｄ／Ａ １０はデジタルヒ′デオイ、τ号をアナログヒ
゛デオ（１１号に変更するデコーダ、同期分ｔｓ４はビ
デオ１０号からフィールド毎の同期を取る回路、メモリ
コントローラ５はテジタルヒ゛デオ（＋’Ｅ号のメモリ
６への＋’Ｆき込み１１７置あるいは読み出すｔ＋’を
置をコントロールしたり、−）き込まれたデシタルビテ
゛オイ、１号を加りして出力するコントローラ、フィー
ルドメモリ６はフィールド！１’−（、ンにデシタルヒ
′デオも１号・を記録するメそり、操作釦９はモートを
いろいろ切換えられる操作釦、係数発生器７はそれぞれ
のモートに応して係数にの値をＩＩｒ変してｌ−に及び
にのイダ番を変えるものである。D/A 10 is a decoder that changes digital video, τ to analog video (no. 11), synchronization component ts4 is a circuit that synchronizes each field from video no. The field memory 6 is a controller that controls the +'F write 117 position or read t+' position into the memory 6, and adds and outputs the stored digital data, No. 1, and the field memory 6. 1'-(, the digital video is also recorded as No. 1. This is to change the Ida number of l- and ni.
ノイズリディーサとしての働きは、ノイズを含んだビデ
オ信号は１乗算部１２で（１−Ｋ）倍に減衰され、加算
回路１３を経てフィールドメモリ６に記録後、乗算部１
１でＫ（Ｑされ加算回路１３へとメモリを含むループを
巡回するか、ノイズは各フレームごとにランタムに人っ
ているのでビデオイ１）号中のノイズ成分だけが抑圧さ
れる。The function of the noise reducer is that the video signal containing noise is attenuated by a factor of (1-K) in the multiplier 12, and after being recorded in the field memory 6 via the adder 13, the video signal containing noise is
Since the noise is generated randomly for each frame, only the noise component in the video signal 1) is suppressed.
（発明か解決しようとする。、！ａ）
この回路構成では静市画と動画のワイプあるいはフェー
ト機能をいれようとすると、カメラ２からのヒ′デ第４
ｊ’ｒ号をフィールドメモリ６に、呻き込むどき処理回
路１４を経由して入力することになる。それゆえ、Ｋ値
の設定をするための準備期間が必要てあり、カメラＪ！
！ ：ｉｅ時、に値の初期値設定等の処理時間かかかり
、ダイレクトフレーズという社な瞬間的な画を扱う場合
に不利になる。(I'm trying to invent or solve it.,!a) With this circuit configuration, if you try to add a wipe or fade function for still images and videos,
j'r number is input to the field memory 6 via the groan processing circuit 14. Therefore, a preparation period is required to set the K value, and camera J!
! : When using ie, processing time is required for initial value setting, etc., which is disadvantageous when dealing with social and instantaneous images such as direct phrases.
本発明は、このような１【悄のもとてなされたもので、
Ｋ値の初期値設定等の処理時間を必要としないヒデオイ
、−号処理装置を提供することを目的とするものである
。The present invention was created out of such 1.
It is an object of the present invention to provide a video processing device that does not require processing time such as setting the initial value of the K value.
（課題を解決するだめの１段）
本発明は、前記＋１的を達成するため、ビデオ化−）処
理装置をつぎのように構成するものである。(One step to solving the problem) In order to achieve the above-mentioned objective, the present invention configures a video processing apparatus as follows.
即ち、デシタルビデオ信号入力端と、デシタルビデオ１
１４号出力端と５ フィールドメモリと、話デジタルビ
デオ（＋Ｋ ”ｊ入力端の信−すとデジタルビデオ１，
１号出力端のイ４；号を切換えて、該フィールドメモリ
に入力する切換スイッチと、該フィールドメモリの出カ
イ１；号と、咳デシタルビデオイ５号入力端の４１１吋
とを入力し夫々に所要の係数をかけて加算し上記テシタ
ルヒデオイハ５＋出力端に出力する処理回路とを備える
ようにする。That is, the digital video signal input terminal and the digital video 1
No. 14 output terminal and 5 field memory, talk digital video (+K"j input terminal signal and digital video 1,
Switch the No. 4 of the No. 1 output terminal and input it to the field memory, and input the output No. 1 of the field memory and the cough digital video No. 411 of the No. 5 input terminal, respectively. A processing circuit for multiplying by a necessary coefficient, adding the result and outputting the result to the output terminal 5+ is provided.
（作用〕
この構成により、切換スイッチをデジタルビデオ入力端
側に切換えてワイプ、フェート動作を行い、す」換スイ
ッチをテシタルヒテ゛オイ１−号出力端側に切換えてノ
イズリデューサ動作を行うことができる。(Function) With this configuration, wipe and fade operations can be performed by switching the changeover switch to the digital video input end side, and noise reducer operation can be performed by switching the changeover switch to the digital video input end side.
以上本発明を実施例により１説明する。 The present invention will be explained above using examples.
第１図は本発明の一実施例のブロック図である。図に於
いて、１は、デジタルビデオ信号入力端のイエ−１号と
処理回路１４の出力即ち、デジタルビデオ入力信号出力
端のイ６−を号とを切換えフィールドメモリ６に供給す
る切換えスイッチ、２はビデオカメラ、３はＡＤコンバ
ータ、４は同期分障回路、５はデジタルビデオ入力信号
のフィールトメそり６への−を込みあるいは読出し０置
を制御したりするメモリコントローラ、６はデシタルビ
デオイ１吃号をフィールド毎に記録するフィールドメモ
リ、７はモートに対Ｊ心して係数にの値を発生させる係
数発生器、８はビデオイ１、号を出力する出力端ｒ、９
はそ一トを変える操伯釦、１０はＤＡコンバータ、１１
．１２．１３は従来と同社の処理回路１４の構成東素で
ある。FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, 1 is a changeover switch that switches between the digital video signal input end No. 1 and the output of the processing circuit 14, that is, the digital video input signal output end No. 6-, and supplies it to the field memory 6; 2 is a video camera, 3 is an AD converter, 4 is a synchronization divider circuit, 5 is a memory controller that controls input or readout of the digital video input signal to the field memory 6, and 6 is a digital video input signal 1. 7 is a coefficient generator that generates a value for the coefficient by centering J on the mote; 8 is an output terminal r that outputs the video number; 9;
10 is the DA converter, 11 is the control button that changes the part.
．． 12.13 is the conventional structure of the processing circuit 14 made by Toso.
この構成で、切換スイッチ１をＡ側に切換えると、第２
図にボ１−従来例と同じ構成となり、ノイズリデューサ
機ｒ）シかｊｉＩられる。With this configuration, when changeover switch 1 is switched to the A side, the second
In the figure, Bo 1 has the same configuration as the conventional example, and a noise reducer is installed.
又、切換スイッチ１をＢ側に倒すと、Ａ／Ｄコンバータ
３からのデジタルビデオ入力信号は切換スイッチの接点
Ｂを介してフィールドメモリ６に入力される。これによ
り静＋Ｌ画をフィールドメモリ６に入力し、この静市画
の（、を号とＡ／Ｄコンバータ３からの動画とを処理回
路１４を通して組合せ、静１１画と動画のワイプやフェ
ート機能かｊｌ−られる。Further, when the changeover switch 1 is turned to the B side, the digital video input signal from the A/D converter 3 is inputted to the field memory 6 via contact B of the changeover switch. As a result, the still image + L image is input to the field memory 6, and the (,) of this still image and the moving image from the A/D converter 3 are combined through the processing circuit 14, and the 11 still images and moving image are wiped or faded. jl- be received.
以１説明したように、本発明によれば、デジタルビデオ
イ１１号入力喘の伝りとデジタルビデ第４Ｓ ”ｊ出力
端の（Ｉｉ号とを切換スイッチにより切換えてフィール
ドメモリに入力するようにしているので、ワイプ、フェ
ード動作の際、切換スイッチを入力端側に切換えること
により０１画取込み時のにイめの初期値設定等の前処理
が不要となる。As explained above, according to the present invention, the transmission of the digital video input No. 11 and the output terminal (Ii of the digital video No. 4S) are switched by a changeover switch so as to be input to the field memory. Therefore, when performing a wipe or fade operation, by switching the selector switch to the input end side, preprocessing such as setting a new initial value at the time of capturing the 01 image becomes unnecessary.
したがって、カメラ［１２時にはシャッタチャンスに強
くなり、又に値の初期値の処理回路が省略でき、回路規
模を小さくできる。Therefore, when the camera is 12 o'clock, it becomes resistant to shutter opportunities, and furthermore, the initial value processing circuit can be omitted, and the circuit scale can be reduced.
第１図は実施例のブロック図、第２図は従来例のブロッ
ク図である。
ｌ・・・・・・切換スイッチ
６・・・・軸フィールドメモリ
１４・・・・・・処理回路FIG. 1 is a block diagram of an embodiment, and FIG. 2 is a block diagram of a conventional example. l...Choice switch 6...Axis field memory 14...Processing circuit
Claims (1)
力端と、フィールドメモリと、該デジタルビデオ信号入
力端の信号とデジタルビデオ信号出力端の信号を切換え
て該フィールドメモリに入力する切換スイッチと、該フ
ィールドメモリの出力信号と該デジタルビデオ信号入力
端の信号とを入力し夫々に所要の係数をかけて加算し上
記デジタルビデオ信号出力端に出力する処理回路とを備
えていることを特徴とするビデオ信号処理装置。a digital video signal input terminal, a digital video signal output terminal, a field memory, a changeover switch that switches between the signal at the digital video signal input terminal and the signal at the digital video signal output terminal and inputs the signal to the field memory; and the field memory. and a processing circuit that inputs the output signal of the digital video signal and the signal of the digital video signal input terminal, multiplies each by a required coefficient, adds the sum, and outputs the resultant signal to the digital video signal output terminal. Device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63273356A JP2732091B2 (en) | 1988-10-31 | 1988-10-31 | Video signal processing device |
| US08/025,737 US5333015A (en) | 1988-10-31 | 1993-03-03 | Image signal processing apparatus having noise eliminating and special effect mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63273356A JP2732091B2 (en) | 1988-10-31 | 1988-10-31 | Video signal processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02121475A true JPH02121475A (en) | 1990-05-09 |
| JP2732091B2 JP2732091B2 (en) | 1998-03-25 |
Family
ID=17526759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63273356A Expired - Lifetime JP2732091B2 (en) | 1988-10-31 | 1988-10-31 | Video signal processing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2732091B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04317277A (en) * | 1990-12-31 | 1992-11-09 | Gold Star Co Ltd | Overlap device of digital television |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2001236005A1 (en) | 2000-02-29 | 2001-09-12 | Chugai Seiyaku Kabushiki Kaisha | Preparations stabilized over long time |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54160550U (en) * | 1978-04-28 | 1979-11-09 | ||
| JPS63114471A (en) * | 1986-10-31 | 1988-05-19 | Sony Corp | Wiper device |
| JPS63211880A (en) * | 1987-02-27 | 1988-09-02 | Hitachi Ltd | Image signal processing device |
-
1988
- 1988-10-31 JP JP63273356A patent/JP2732091B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54160550U (en) * | 1978-04-28 | 1979-11-09 | ||
| JPS63114471A (en) * | 1986-10-31 | 1988-05-19 | Sony Corp | Wiper device |
| JPS63211880A (en) * | 1987-02-27 | 1988-09-02 | Hitachi Ltd | Image signal processing device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04317277A (en) * | 1990-12-31 | 1992-11-09 | Gold Star Co Ltd | Overlap device of digital television |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2732091B2 (en) | 1998-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4249212A (en) | Television picture special effects system using digital memory techniques | |
| CA1260605A (en) | Standard converting apparatus | |
| EP0343728A1 (en) | Method of and arrangement for motion detection in an interlaced television picture obtained after film-to-television conversion | |
| EP0487605B1 (en) | Image reversing unit | |
| JPS62213386A (en) | Picture signal coupler | |
| KR0167799B1 (en) | Video signal compressor | |
| GB1326386A (en) | Television standards conversion | |
| JPH0686316A (en) | Apparatus for video special effect | |
| KR900007246A (en) | Method and apparatus for converting temporal ratio of high definition television images | |
| JPH06217264A (en) | Image signal converting circuit | |
| US4137549A (en) | DPCM Coding apparatus | |
| JP2732091B2 (en) | Video signal processing device | |
| JPS5853826B2 (en) | Image signal processing device | |
| JPS59193673A (en) | Television system having scanning line reference converter | |
| JP2846427B2 (en) | PAL signal / CIF signal conversion circuit | |
| JP2959055B2 (en) | Video signal switching device | |
| JPH03102982A (en) | Special effect device | |
| KR0137359B1 (en) | Method of steeling picture in vtr and device | |
| KR0151442B1 (en) | Display control circuit of television receiver | |
| JPH03114096A (en) | Image decoding device | |
| KR920001160B1 (en) | On-screen text recording circuit during video tape recorder recording | |
| JPS63107388A (en) | Image storage device | |
| JPS5939182A (en) | Frame memory circuit | |
| JPS6013591B2 (en) | Multi-point scanning method | |
| JPS60111581A (en) | Processor of still picture signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081226 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term |