JPH02129914A - Heat treatment of compound semiconductor wafer - Google Patents

Abstract

PURPOSE:To acquire a uniform activation rate on the surface of a wafer by changing a partial pressure of AsH3 gas according to a heat treatment temperature. CONSTITUTION:In a series of heat treatment processes of temperature-up, high temperature holding and temperature-down; at first, AsH3 gas partial pressure is increased as a temperature is made to rise in the temperature-up process, secondly, AsH3 gas partial pressure is held constant in the high temperature holding state, and the AsH3 gas partial pressure is reduced according as a temperature lowers in the last temperature-down process. Concrete relationship between the temperature and the AsH3 gas partial pressure is determined by a dissociation pressure of As on a surface of a compound semiconductor wafer. Since an excessive As pressure is not thereby applied to a surface of a wafer as compared to a dissociation pressure of As in an area near the wafer surface does not vary or defects does not develop. Abnormal diffusion of impurity and dispersion of activation rates can be prevented in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Statement of the Invention (Field of Industrial Application) The present invention relates to a method for heat treating compound semiconductor wafers.

(Prior Art) In the manufacturing process of compound semiconductor devices such as GaAs, high-temperature heat treatment of 800° C. or higher is sometimes performed in the wafer state. For example, ion-implanted impurities may be activated. In such heat treatment, As is added to the wafer surface in order to prevent the dissociation of As from the wafer surface.
You have to apply pressure. For this purpose, a method of performing heat treatment in arsine (A s Ha ) gas is sometimes adopted.

By the way, when performing such heat treatment, a sea fence is often adopted in which the wafer is placed in an open-tube electric furnace, and the temperature is raised, maintained at high temperature, and lowered without flowing A s Hs gas.

In this conventional heat treatment method, A s Hs in the furnace tube
Gas partial pressure was always constant. That is, in a series of processes such as setting up the wafer, raising the temperature, performing high-temperature heat treatment, and lowering the temperature, the A s Ha gas partial pressure was always constant (FIG. 3).

The As H3 gas partial pressure at this time was determined as a value necessary to prevent dissociation of As from the wafer surface at the highest temperature. However, in a temperature state other than the high-temperature holding state, for example, in a temperature-lowering process state, this A s Ha gas partial pressure becomes an unnecessarily large value. In other words, an As pressure far greater than the As dissociation pressure on the GaAs wafer surface is applied to the wafer surface. In this method, the stoichiometry near the wafer surface fluctuates due to excessive As pressure being applied to the wafer surface, resulting in A
A s-rlch state appears. As a result, crystal defects occur near the surface, which further causes abnormal diffusion of impurities and variations in activation rate.

(Problems to be Solved by the Invention) In a heat treatment method in which As pressure is applied to the surface of a compound semiconductor wafer such as GaAs by flowing As Ha gas, and high temperature heat treatment is performed while preventing the dissociation of As from the surface,
Crystal defects occur near the wafer surface because excessive As pressure is applied to the wafer surface at low temperatures before and after high-temperature heat treatment. This causes problems such as abnormal diffusion of impurities and variations in activation rate.

[Structure of the Invention] (Means for Solving the Problem) In order to solve the above problem, A s in the furnace is adjusted according to the temperature in the furnace (approximately equal to the temperature of the compound semiconductor wafer).
It is characterized by performing a series of heat treatment steps by adjusting the partial pressure of Ha gas.

In other words, in a series of heat treatment steps of raising temperature, holding high temperature, and lowering temperature, first in the temperature raising process, as the temperature is raised, A
The s H3 gas partial pressure is increased, then the A s Hs gas partial pressure is kept constant in the high temperature holding state, and the A s Ha gas partial pressure is decreased as the temperature decreases in the final cooling process. The specific relationship between temperature and As Hs gas partial pressure is determined by the dissociation pressure of As on the surface of the compound semiconductor wafer.

A thin film such as 5i02 is formed on the wafer surface,
This functional relationship changes when As pressure is applied through the thin film.

(Function) According to the present invention, since an excessive As pressure compared to the dissociation pressure of As is not applied to the wafer surface, the stoichiometry near the wafer surface does not change or defects occur. Therefore, various problems caused by this can be solved.

(Example) Hereinafter, the details of the present invention will be explained using examples.

In this example, a GaAs wafer was placed in an open-tube electric furnace and heat treated. A s H from the gas inlet
A mixed gas of 3 gas and Ar gas was flowed, and the exhaust side was connected to an exclusion device. The inside of the furnace is maintained at atmospheric pressure. A s H
The A s Ha gas partial pressure was adjusted by the mixing ratio of the a gas.

FIG. 1 shows the temperature sea fence in a series of heat treatment steps. In this example, the temperature was raised almost linearly from room temperature to 820°C in 30 minutes, and 820°C was raised to 20°C.
After holding the temperature for 60 minutes, the temperature was lowered to 300°C.

FIG. 2 shows the A s H3 gas partial pressure in the furnace versus the heat treatment temperature.

This method reduced the etch bits observed in KOH etching at a depth of 2 μm or less from the surface of the GaAs substrate. Also, this method was employed to activate the ion implantation layer to fabricate a MESFET. The MPSFET is a self-line type using a WNx gate, and the ion implantation condition for the channel layer is 40 KeV.

The size was 5×10 cm. When the variation in VTH within a 3-inch wafer was investigated using this MESPET, σVTII was approximately half that of the conventional method.

[Effects of the Invention] As described above, according to the present invention, the stoichiometry of the wafer surface does not change during the heat treatment process performed under As pressure, and a uniform activation rate can be obtained on the wafer surface. Can be done.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a temperature sea fence according to an embodiment of the present invention, and FIG. 2 is a diagram showing a temperature sea fence according to an embodiment of the present invention.
A diagram showing the Hs gas partial pressure, Fig. 3 is a diagram showing the Hs gas partial pressure.
It is a figure showing Hs gas partial pressure. → 5 (intermediate) Figure 11 ÷ example 1t 丞game (°C)

Claims (1)

[Claims] A method for heat treatment of compound semiconductor wafers, characterized in that the partial pressure of AsH_3 gas is changed according to the heat treatment temperature in an apparatus for heat-treating compound semiconductor wafers in an AsH_3 atmosphere.