JPH02130039U

JPH02130039U -

Info

Publication number: JPH02130039U
Application number: JP3932989U
Authority: JP
Priority date: 1989-04-03
Filing date: 1989-04-03
Publication date: 1990-10-26

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例による計算機を示
す構成図、第２図はこの考案の計算機におけるマ
イクロプログラムの処理シーケンスのフローチヤ
ート、第３図は従来の計算機の構成図、第４図は
従来の計算機におけるマイクロプログラムの処理
シーケンスのフローチヤートである。図において、１……主記憶部、２……マイクロ
ＲＯＭ部、３……中央演算処理部、４……マツプ
ＲＯＭ部、５……セレクタ、６……アドレスカウ
ンタ、７……マイクロ履歴ＲＡＭ部である。なお
、図中同一あるいは相当部分には同一符号を付し
て示してある。 Fig. 1 is a block diagram showing a computer according to an embodiment of this invention, Fig. 2 is a flowchart of a microprogram processing sequence in the computer of this invention, Fig. 3 is a block diagram of a conventional computer, and Fig. 4 is a block diagram showing a computer according to an embodiment of this invention. 1 is a flowchart of a microprogram processing sequence in a conventional computer. In the figure, 1...Main storage unit, 2...Micro ROM unit, 3...Central processing unit, 4...Map ROM unit, 5...Selector, 6...Address counter, 7...Micro history RAM unit It is. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.

Claims

[Scope of utility model registration request]

A main memory section that stores programs that perform predetermined tasks, a central processing section that executes instructions called from the main memory section and has arithmetic capabilities, and a central processing section that carries out processing for this central processing section. a micro-fixed memory processing unit that stores sequences, a map-fixed memory unit that stores a start address of a microprogram to be processed for the instructions for the micro-fixed memory unit, and a central processing unit. In a computer equipped with a selector for selecting either the calculation result or the start address output from the map fixed storage unit, only when the calculation address of the central processing unit is other than the previous calculation address plus 1, the execution address an address counter that constantly shows the minimum address to the maximum address,
The execution address itself can be written to the address indicated by the address counter,
and, when an abnormality occurs in the processing sequence of the microprogram, means for retaining the processing sequence of the microprogram up to the occurrence of the abnormality as a history of the start address of the microprogram of the instruction.