JPH02133749U - - Google Patents
Info
- Publication number
- JPH02133749U JPH02133749U JP4020389U JP4020389U JPH02133749U JP H02133749 U JPH02133749 U JP H02133749U JP 4020389 U JP4020389 U JP 4020389U JP 4020389 U JP4020389 U JP 4020389U JP H02133749 U JPH02133749 U JP H02133749U
- Authority
- JP
- Japan
- Prior art keywords
- microprogram
- register
- memory
- sequencer
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図はこの考案の一実施例によるマイクロプ
ログラムシーケンサを示す図、第２図は従来のマ
イクロプログラムシーケンサを説明するための図
である。
図中、１は命令レジスタ、２はマツプメモリ、
３はセレクタ、４はマイクロプログラムアドレス
レジスタ、５はマイクロプログラムメモリ、６は
マイクロ命令レジスタ、７は加算器、８はスタツ
クレジスタ、９はセレクタ、１０は加算器、１１
はアキユムレータである。なお、図中、同一部分
又は相当部分には同一符号を付してある。
FIG. 1 is a diagram showing a microprogram sequencer according to an embodiment of this invention, and FIG. 2 is a diagram for explaining a conventional microprogram sequencer. In the figure, 1 is an instruction register, 2 is a map memory,
3 is a selector, 4 is a microprogram address register, 5 is a microprogram memory, 6 is a microinstruction register, 7 is an adder, 8 is a stack register, 9 is a selector, 10 is an adder, 11
is an accumulator. In addition, in the figures, the same parts or corresponding parts are given the same reference numerals.
Claims (1)
クロプログラムシーケンサにおいて、処理内容を
規定する命令レジスタにシリアルにシフトインす
る手段と、マイクロプログラムアドレスレジスタ
の内容を累算する加算器及びアキユムレータと、
マイクロプログラムメモリの出力を累算する加算
器及びアキユムレータと、マイクロ命令レジスタ
にシリアルにシフトインする手段と、チエツクサ
ムデータを有するマイクロプログラムメモリとを
有し、命令レジスタに格納された処理のマイクロ
プログラムの先頭アドレスを格納したマツプメモ
リにチエツクサムデータを付加した事を特徴とす
るマイクロプログラムシーケンサ。 In a microprogram sequencer that controls the execution order of microprograms, means for serially shifting into an instruction register that defines processing contents, an adder and an accumulator that accumulate the contents of the microprogram address register,
A microprogram for processing stored in the instruction register, comprising an adder and an accumulator for accumulating the output of the microprogram memory, means for serially shifting into the microinstruction register, and a microprogram memory having checksum data. A microprogram sequencer characterized in that checksum data is added to a map memory that stores the start address of a microprogram sequencer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4020389U JPH02133749U (en) | 1989-04-05 | 1989-04-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4020389U JPH02133749U (en) | 1989-04-05 | 1989-04-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02133749U true JPH02133749U (en) | 1990-11-06 |
Family
ID=31549788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4020389U Pending JPH02133749U (en) | 1989-04-05 | 1989-04-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02133749U (en) |
-
1989
- 1989-04-05 JP JP4020389U patent/JPH02133749U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02133749U (en) | ||
| JPH0386452U (en) | ||
| JPS6389146U (en) | ||
| JPS6429918U (en) | ||
| JPS63147742U (en) | ||
| JPS6452064U (en) | ||
| JPH01164550U (en) | ||
| JPS6335139U (en) | ||
| JPS6312232U (en) | ||
| JPH05151369A (en) | Integrated circuit | |
| JPS6452004U (en) | ||
| JPS6281151U (en) | ||
| JPH0393905U (en) | ||
| JPS63163043U (en) | ||
| JPH02138305U (en) | ||
| JPH03119238U (en) | ||
| JPS6452063U (en) | ||
| JPS614242U (en) | Image information processing device | |
| JPS62146223U (en) | ||
| JPH0284949U (en) | ||
| JPS6047057U (en) | Peripheral control device | |
| JPS60116539U (en) | data processing system | |
| JPS6025050U (en) | Multiple program management device | |
| JPS59147247U (en) | Interrupt vector conversion circuit in computer system | |
| JPH0452247U (en) |