JPH02133923A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH02133923A
JPH02133923A JP28746588A JP28746588A JPH02133923A JP H02133923 A JPH02133923 A JP H02133923A JP 28746588 A JP28746588 A JP 28746588A JP 28746588 A JP28746588 A JP 28746588A JP H02133923 A JPH02133923 A JP H02133923A
Authority
JP
Japan
Prior art keywords
metal
semiconductor device
film
manufacturing
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28746588A
Other languages
Japanese (ja)
Other versions
JP2697796B2 (en
Inventor
Kenichi Kubo
久保 謙一
Jiro Katsuki
二郎 勝木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP63287465A priority Critical patent/JP2697796B2/en
Publication of JPH02133923A publication Critical patent/JPH02133923A/en
Application granted granted Critical
Publication of JP2697796B2 publication Critical patent/JP2697796B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、半導体装置の製造方法に関するもので,特に
急峻な側面をもつコンタクトホール、スルーホール上に
形成された配線パターンの平坦化方法に関するものであ
る。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device, and in particular a wiring pattern formed on a contact hole or a through hole with steep sides. The present invention relates to a flattening method.

(従来の技術) 半導体集積回路の製造において配線技術、例えば半導体
素子の多層配線技術において、コンタクトホール又はス
ルーホール等をアルミニウム(Aff)等の配線用金属
を埋め込み,且つ凸凹のある段差部などを平坦化する技
術としてバイアススバッタ方法がある0例えば、IEE
E PROCEEDINGS OF THEINTER
NATIONAL  ELEC:TR0N  DEVI
CES  MEETING  DEC7−101986
P70〜73に開示された方法がある。即ち、第二図に
示すように真空槽に基板を導入する前に付着した基板表
面の酸素等の不純物ガスの放出による膜質の劣化及びコ
ンタクトホール下部のWI撃によるダメージを防ぐため
、第二図(A)に示すような半導体基板、例えば、Si
基板(11)上のシリコン酸化物(SiO,)(12)
に設けられた開口部(13)に、1ステツプ目として通
常のスパッタ方法で第二図に示すようにアルミニウム又
はアルミニウム合金又は高融点金属及び、そのシリサイ
ドの下地膜(14)をSi基板(11)に成膜し、2ス
テツプ目をバイアススパッタ法により、第二図(C)に
示すようにアルミニウム又はアルミニウム合金をSi基
板(11)を加熱状態で成膜し、バイアスによる加熱効
果とイオン衝撃によりAn又はAj2合金の融点より低
い温度で表面張力等のPによりコンタクトホール内にA
2又はA2合金を流動させ埋め込むものである。
(Prior art) In wiring technology in the manufacture of semiconductor integrated circuits, for example, multilayer wiring technology for semiconductor elements, contact holes or through holes are filled with wiring metal such as aluminum (Aff), and uneven stepped portions, etc. There is a bias scattering method as a planarization technique. For example, IEE
E PROCEEDINGS OF THEINTER
NATIONAL ELEC:TR0N DEVI
CES MEETING DEC7-101986
There is a method disclosed in P70-73. That is, as shown in Fig. 2, in order to prevent the deterioration of the film quality due to the release of impurity gas such as oxygen that adhered to the surface of the substrate before introducing the substrate into the vacuum chamber, and the damage caused by WI impact at the bottom of the contact hole, A semiconductor substrate as shown in (A), for example, Si
Silicon oxide (SiO,) (12) on substrate (11)
As a first step, a base film (14) of aluminum or aluminum alloy or high melting point metal and its silicide is applied to the opening (13) of the Si substrate (11) using a normal sputtering method as shown in FIG. ), and in the second step, as shown in Figure 2 (C), aluminum or aluminum alloy is deposited as a film on the Si substrate (11) in a heated state by bias sputtering, and the heating effect due to bias and ion bombardment are Due to P such as surface tension at a temperature lower than the melting point of An or Aj2 alloy, A is formed in the contact hole.
2 or A2 alloy is flowed and embedded.

又、上記の他に開口部を埋め込む方法とじてF126 
 SEMICONDUCTORINTERNATION
AL  9/1987jやfi’ SEMICON J
APAN ’86 TECHNICAL SYMPO5
IUMTOKYO,JAPAN、Decll−1219
86“PLANARIZATION 0FAL  AL
LOY  METALIZATION  BY  5I
IRFACE  5ELF−DIFF−USION”j
に開示された技術もある。
In addition to the above, there is also a method of embedding the opening, F126.
SEMICONDUCTOR INTERNATION
AL 9/1987j and fi' SEMICON J
APAN '86 TECHNICAL SYMPO5
IUMTOKYO, JAPAN, Decll-1219
86 “PLANARIZATION 0 FAL AL
LOY METALIZATION BY 5I
IRFACE 5ELF-DIFF-USION"j
There are also technologies disclosed in

(発明が解決しようとする課M) しかしながら上記従来方法には次のような問題点がある
。先ず、前者の2ステツプ方法にて形成するプロセスに
おいて1層目(1ステツプ目)にアルミニウム又はアル
ミニウム合金を使用する手段では、膜厚が薄いと島状(
16)に成長しやすくなる原因と成りやすい、(第三図
(A))特に、コンタクトホールの凹部が小さい微細化
素子では1ステツプ目のメタルの膜厚を厚くしすぎると
凹部上端(41)で第四図(A)に示す如くブリッジ(
42)を形成し、この上に第二の工程でアルミ層(工5
)をバイアススパッタすると、コンタクトホール(13
)内に第四図(B)の如く空胴(43)が生じやすい問
題があった。第四図(B)の他の現象として第五図(E
)、(F)に開示されたようにコンタクトホール(13
)の側壁に被着しない場合や、一方壁面のみに被着する
場合がある。また、前者の2ステツプ方法で形成するプ
ロセスにおいて、1ステツプ目に高融点金属を使用する
手段では膜厚が薄いとピンホール等の欠陥が発生し充分
に下地からバイアススパッタ中に発生する酸素等のガス
を防ぐことが不可能であった。また、後者のコンタクト
ホールの濡れ性を改善する手段として、高融点金属のT
iVを薄く堆積させた後、アルミ層をバイアススパッタ
リングする方法であるが、TiWl15にアルミ層を形
成するとき、TiV股を通して下地からの不純物ガスの
発生による膜質の劣化等により、上記した第三図(A)
のようにアルミ層が島状に被着したり、粒径が大きくな
り平坦性に欠け、尚且つ粒界にボイドが発生するという
問題があった。また、アルミ層に^Q−5i合金を使用
した場合、シリコンノジュールが生じ、後に続く工程で
パターンを形成する際、エツチングしにくいという問題
があった。また、開口部を埋め込む方法として、再スパ
ツタ効果を利用した方法が、J、 ELECTROCH
EM、 SOC,5OLIDSTATE  5CIEN
CE  AND  TECHNOLOGY  JUNE
  1985  P1466〜1472に開示されてい
る。しかしこの方法は、開口部が閉鎖されない膜厚程度
に成膜し、この成膜をスパッタによる膜の被着とバイア
ススパッタによる食刻作用(エツチング)により埋め込
むため時間が長くかかるという問題がある。
(Problem M to be solved by the invention) However, the above conventional method has the following problems. First, in the former two-step process, when aluminum or aluminum alloy is used for the first layer (first step), if the film is thin, it will form an island (
16) (Figure 3 (A)) In particular, in miniaturized elements where the contact hole recess is small, if the metal film thickness in the first step is made too thick, the upper end of the recess (41) As shown in Figure 4 (A), the bridge (
42), and on top of this, an aluminum layer (step 5) is formed in the second step.
) is bias sputtered, a contact hole (13
) There was a problem in that a cavity (43) as shown in FIG. 4 (B) was likely to occur. Another phenomenon in Figure 4 (B) is Figure 5 (E
), (F), the contact hole (13
) may not adhere to the side walls, or may adhere only to one wall surface. In addition, in the former two-step process, if a high-melting point metal is used in the first step, defects such as pinholes will occur if the film is thin, and oxygen, which is generated during bias sputtering from the base layer, etc. It was impossible to prevent the gas. In addition, as a means to improve the wettability of the latter contact hole, T
This method involves bias sputtering an aluminum layer after depositing a thin layer of iV, but when forming an aluminum layer on TiWl15, the film quality deteriorates due to the generation of impurity gas from the base through the TiV crotch, resulting in the problem shown in Figure 3 above. (A)
There were problems in that the aluminum layer was deposited in island-like form, the grain size became large and lacked flatness, and voids were generated at the grain boundaries. Further, when Q-5i alloy is used for the aluminum layer, silicon nodules are generated, making it difficult to etch when forming a pattern in a subsequent step. In addition, as a method of embedding the opening, a method using the resputtering effect is described in J. ELECTROCH.
EM、SOC、5OLIDSTATE 5CIEN
CE AND TECHNOLOGY JUNE
1985 P1466-1472. However, this method has a problem in that it takes a long time because the film is formed to a thickness that does not close the opening, and the film is filled in by deposition by sputtering and etching by bias sputtering.

本発明は上述の従来技術事情に対処してなされたもので
プロセス条件の範囲が広く、良好なカバレージが得られ
、かつ高品質の金属の凹部への埋め込みが可能な半導体
装置の製造方法を提供しようとするものである。
The present invention has been made in response to the above-mentioned prior art situation, and provides a method for manufacturing a semiconductor device that has a wide range of process conditions, can obtain good coverage, and can fill recesses with high-quality metal. This is what I am trying to do.

〔発明の構成〕[Structure of the invention]

(iillgを解決するための手段) この発明は、基板表面の凹部に金属を埋込む半導体装置
の製造方法1こおいて、上記凹部を含む表面にSi基板
と^a又はi合金間の反応を防ぐ効果のあるいわゆる拡
散バリアメタルとして高融点の第一の金属を堆積させる
第一の工程と、上記第一の膜の上にチタン(Ti)を上
記凹部が閉鎖されない程度の膜厚に堆積させる第二の工
程と、上記凹部に上記第−の金属およびチタンより低ぶ
:点の第三の金属をバイアススパッタする第三の工程と
を具備してなることを特徴とする。
(Means for Solving Iillg) The present invention provides a semiconductor device manufacturing method 1 in which a metal is buried in a recessed portion of a substrate surface, in which a reaction between a Si substrate and an ^a or i alloy is applied to the surface including the recessed portion. A first step of depositing a first metal with a high melting point as a so-called diffusion barrier metal that has the effect of preventing diffusion, and depositing titanium (Ti) on the first film to a thickness such that the recesses are not closed. The method is characterized by comprising a second step and a third step of bias-sputtering the third metal and a third metal having a lower diameter than titanium into the recessed portion.

(作用動床) 基板表面の凹部に金属を埋め込む半導体装置の製造方法
において、上記凹部を含む表面に高融点の第一の金属を
堆積させる第一の]工程と、上記第一の膜の上にチタン
(Ti)を上記凹部が閉鎖さ才しない程度の膜厚に堆積
させる第二の工程と、上記四部に上記第一の金属および
チタンより低融点の第三の金属をバイアススパッタする
第三の一1″、稈とを具備したことにより、チタン(T
i)のゲッタリング効果で、第一の金属1蘭からの不純
物の発生を防止し、また、第三の金属を形成する時に発
生するシリコン(Si)の偏析を防止し、また粒径を小
さく形成でき、凸凹のある部分の形状が滑らかでLlつ
表面が平坦な金7ml漠が形成可能となる。
(Working bed) In a method for manufacturing a semiconductor device in which metal is embedded in a recess on a substrate surface, a first step of depositing a first metal with a high melting point on the surface including the recess, and a step on the first film described above. a second step of depositing titanium (Ti) to a thickness that does not close the recess, and a third step of bias sputtering the first metal and a third metal having a lower melting point than titanium on the four parts. Titanium (T
The gettering effect of i) prevents the generation of impurities from the first metal, prevents the segregation of silicon (Si) that occurs when forming the third metal, and reduces the particle size. It is possible to form 7 ml of gold with a smooth shape in the uneven part and a flat surface.

(実施例9 以下、本発明半導体装置の製造方法の一実施例を図面を
参照して説明する。
(Embodiment 9 An embodiment of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings.

半導体基板例えば、シリコン(Si)の半導体ウェハ0
表面に形成された二酸化シリコン膜などの絶縁層■には
凹部例えば、開口部が半導体ウェハ0表面を露出して設
けられていて、この開口部はコンタクトホール■と呼ば
れている。このホール■に、特に上記半導体ウェハ■を
予め加熱すること無く、第一の金属、例えば高融点金属
チタンの窒化物である窒化チタン(TiN)膜に)を第
1図(A)に示す如く厚さ、例えば数100人〜300
0人程度に一層目即ち金属間の拡散障壁層であるバリア
メタルとして通常行なわれているスパッタリングにて堆
積させる(第一の工程)、この場合スパーツタリングに
よりウェハ■の温度の上昇はありうる。この時、二酸化
シリコン膜■の表面にも一層目バリアメタルに)は薄く
形成される。この時半導体ウェハ■は予め加熱例えば3
00℃にしても良い。
Semiconductor substrate, for example, a silicon (Si) semiconductor wafer 0
An insulating layer (2) such as a silicon dioxide film formed on the surface is provided with a recess, for example, an opening exposing the surface of the semiconductor wafer 0, and this opening is called a contact hole (2). Into this hole (2), without preheating the semiconductor wafer (2), a first metal (for example, a titanium nitride (TiN) film, which is a nitride of high melting point metal titanium) is deposited as shown in FIG. 1(A). Thickness, for example several 100 to 300
The first layer, that is, the barrier metal, which is a diffusion barrier layer between metals, is deposited on approximately 0 people by the usual sputtering process (first step). In this case, the temperature of the wafer may increase due to sputtering. . At this time, a thin first layer (barrier metal) is also formed on the surface of the silicon dioxide film (2). At this time, the semiconductor wafer ■ is preheated, e.g.
It may be set to 00°C.

次に、第二の工程として第一図(B)のように上記−層
バリアメタルに)から発生する不純物の防止及び次の第
三工程におけるバイアススパッタリング法によるアルミ
膜形成時に発生するシリコンの偏析や段差部に発生しゃ
すいボイドを防止するためにゲッタリング効果のあるチ
タン(Ti)層0を上記コンタクトホール(3)が閉鎖
されない程度の厚さ数10〜数100人程度の厚さに、
例えば通常行なわれているスパッタリング法にて堆積さ
せる。次に第三の工程として第一図(C)のように上記
チタンの層■の上にさらにこのチタン層0及び上記第一
のバリアメタルに)より低融点の金属例えばアルミニウ
ム層(0を形成する。ここで、この工程は、アスペクト
比が大きくともステップカバレージを良くするために例
えば、半導体基板■を予め200℃以下5例えば100
’C程度の加熱状態で半導体基板■にRFバイアス、例
えば自己バイアス電圧300Voltを印加し且つ10
0℃から400℃に昇温してからヌは、昇温しながらス
パッタリングしてアルミ層■を堆積させる。
Next, as a second step, as shown in Figure 1 (B), the prevention of impurities generated from the above-mentioned layer barrier metal and the segregation of silicon that occurs during aluminum film formation by bias sputtering method in the third step. In order to prevent voids that may occur in the step portions, a titanium (Ti) layer 0 having a gettering effect is coated to a thickness of several tens to several hundreds of layers so that the contact hole (3) is not closed.
For example, it is deposited by a commonly used sputtering method. Next, as a third step, as shown in FIG. Here, in this step, in order to improve step coverage even if the aspect ratio is large, for example, the semiconductor substrate
RF bias, for example, a self-bias voltage of 300 Volt, is applied to the semiconductor substrate (2) in a heated state of about 10°C, and
After raising the temperature from 0° C. to 400° C., sputtering is performed while increasing the temperature to deposit an aluminum layer (1).

即ちこのようなバイアススパッタ方法によるとまず初め
に低温で^Q膜が堆積するため微細な開口部であるコン
タクトホールの側面に島状成長することなしに半導体基
板全面を覆いさらに基板加熱機構(例えば、基板加熱機
構単独では約60秒で設定温度に昇温)で加熱し、かつ
RFバイアスによる加熱効果とアルゴンイオンによるA
Q結晶への欠陥及び歪み等を促進し八〇の融点以下で流
動又は変形しやすくするためアルミニウムはコンタクト
ホール(3)内に向かってスムーズに移動して上記コン
タクトホール■を埋め尽くすことができる。
That is, according to such a bias sputtering method, the ^Q film is first deposited at a low temperature, so that it covers the entire surface of the semiconductor substrate without forming an island-like growth on the side surface of the contact hole, which is a fine opening. , the temperature rises to the set temperature in about 60 seconds using the substrate heating mechanism alone), and the heating effect due to RF bias and A due to argon ions.
In order to promote defects and distortions in the Q crystal and to make it easier to flow or deform below the melting point of 80, the aluminum can move smoothly into the contact hole (3) and fill the contact hole (■). .

上記第一、第二、第三の工程は大気に晒すこと無く連続
的に実行する手段と同様の効果が得られる手段として第
一の工程と第二の工程の間に基板を大気に晒して不連続
に実行する手段がある。
The above first, second, and third steps are performed continuously without being exposed to the atmosphere, and as a means to obtain the same effect, the substrate is exposed to the atmosphere between the first and second steps. There is a way to execute it discontinuously.

又、上記第一、第二、第三の工程は大気に晒すこと無く
、シングルチャンバーもしくは各処理室が独立したいわ
ゆるマルチチャンバーから成る成膜装置で処理をしても
よい。
Further, the first, second, and third steps may be performed in a film forming apparatus consisting of a single chamber or a so-called multi-chamber in which each processing chamber is independent, without being exposed to the atmosphere.

上記実施例のように基板ω上に形成されたコンタクトホ
ール等の凹部に配線パターンを形成する際に第−層とし
てバリアメタル層(イ)上にチタンのWJ■を堆積させ
、このチタンの層■上にアルミの層0をバイアススパッ
タ法で堆積させると第六図に示すように例えばアルミ層
が形成でき第八図に示す従来のチタン層を含まないバイ
アススパッタ法で堆積されたアルミ層と比較するとチタ
ンの効果によりアルミ合金のグレインサイズ(粒径)を
小さくでき粒界に発生するシリコンの異状析出やボイド
等の欠陥が無くなり表面が滑らかになる。
As in the above embodiment, when forming a wiring pattern in a recess such as a contact hole formed on the substrate ω, a titanium WJ is deposited on the barrier metal layer (a) as the -th layer, and this titanium layer is ■If an aluminum layer 0 is deposited on top by bias sputtering, an aluminum layer, for example, is formed as shown in Figure 6, and it is different from the conventional aluminum layer deposited by bias sputtering, which does not include a titanium layer, as shown in Figure 8. In comparison, the effect of titanium can reduce the grain size of aluminum alloys, eliminate defects such as abnormal silicon precipitation and voids that occur at grain boundaries, and create a smooth surface.

又、本実施例では1.0ミクロン径のアスペクト比1で
完全平坦化が可能であった。さらに、第七図に示す従来
のチタン層を含まない通常のバイアスをかけないスパッ
タ法で堆積されたアルミ層と比較しても、さらに膜質が
向上したことがわがる。
Further, in this example, complete flattening was possible with a diameter of 1.0 microns and an aspect ratio of 1. Furthermore, it can be seen that the film quality is further improved compared to the conventional aluminum layer deposited by sputtering without applying a bias, which does not include a conventional titanium layer, as shown in FIG.

この発明は上記実施例に限定されるものではなく第一工
程で堆積される金5!膜は、高融点の金属膜ならいずれ
でも良く、例えばW又はTiVやシリサイド系ノMoS
ix、 WSi、 TiSi、 TaSiなどでも良く
、第三工程でバイアススパッタにより堆積させる金属も
2元系以上のアルミ合金でも良く、上記実施例と同様の
効果が得られる。
This invention is not limited to the above embodiment, but the gold 5! deposited in the first step! The film may be any metal film with a high melting point, such as W, TiV, or silicide-based MoS.
ix, WSi, TiSi, TaSi, etc., and the metal deposited by bias sputtering in the third step may also be an aluminum alloy of two or more elements, and the same effect as in the above embodiment can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第一図は本発明方法の一実施例を説明するための図1.
第二図は従半方法を説明するための図、第三、第四、第
五図は第二図方法による問題点説明図、第六図は第一図
方法により形成されるアルミ膜の表面の結晶構造を表わ
す図、第七図および第八図は従来方法により形成された
アルミ膜の表面の結晶構造を表わす図である。 1・・・シリコン基板  2・・・酸化膜3・・・コン
トクトホール 4・・・第一の金属膜(パリアメクル)5・・・チタン
膜    6・・・アルミニウム膜特許出願人 東京エ
レクトロン株式会社第1図 第3図 (A) (B) 第2図 財 4 (田 (A) (8ン (C) (A) 図 (A) (E) 妃 t 1? I這 γ 背 1図
Figure 1 is for explaining an embodiment of the method of the present invention.
Figure 2 is a diagram to explain the secondary method; Figures 3, 4, and 5 are diagrams explaining problems caused by the method in Figure 2; Figure 6 is the surface of the aluminum film formed by the method in Figure 1. Figures 7 and 8 are diagrams representing the crystal structure of the surface of an aluminum film formed by the conventional method. 1...Silicon substrate 2...Oxide film 3...Contact hole 4...First metal film (pariamekuru) 5...Titanium film 6...Aluminum film Patent applicant Tokyo Electron Ltd. Figure 1 Figure 3 (A) (B) Figure 2 Property 4 (田 (A) (8 ん (C) (A) Figure (A) (E) Queen t 1? I crawl γ back 1 figure

Claims (5)

【特許請求の範囲】[Claims] (1)基板表面の凹部に金属を埋め込む半導体装置の製
造方法において、上記凹部を含む表面に高融点金属の第
一の金属を堆積させる第一の工程と、上記第一の膜の上
にチタン(Ti)を上記凹部が閉鎖されない程度の膜厚
に堆積させる第二の工程と、上記凹部にチタンより低融
点の第三の金属をバイアススパッタする第三の工程とを
具備してなることを特徴とする半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device in which a metal is embedded in a recess on a substrate surface, including a first step of depositing a first metal, which is a high-melting point metal, on the surface including the recess, and a titanium film on the first film. a second step of depositing (Ti) to a thickness that does not close the recess; and a third step of bias sputtering a third metal having a lower melting point than titanium into the recess. A method for manufacturing a featured semiconductor device.
(2)第一の金属は窒化チタン又は高融点シリサイドか
ら成る拡散バリアメタルであることを特徴とする請求項
1記載の半導体装置の製造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the first metal is a diffusion barrier metal made of titanium nitride or high melting point silicide.
(3)第三の金属は同一種類のアルミニウム又はアルミ
ニウム合金であることを特徴とする請求項1記載の半導
体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, wherein the third metal is the same type of aluminum or aluminum alloy.
(4)第一、二、三の金属は各工程間で大気に晒すこと
なく、シングルチャンバーもしくは各処理室が独立した
いわゆるマルチチャンバーから成る成膜装置で処理され
ることを特徴とする請求項1記載の半導体装置の製造方
法。
(4) A claim characterized in that the first, second, and third metals are processed in a film forming apparatus consisting of a single chamber or a so-called multi-chamber in which each processing chamber is independent, without being exposed to the atmosphere between each process. 1. The method for manufacturing a semiconductor device according to 1.
(5)第一の金属と第二、三の金属の工程間で大気に晒
して処理されることを特徴とする請求項1記載の半導体
装置の製造方法。
(5) The method of manufacturing a semiconductor device according to claim 1, wherein the process is performed by exposing the first metal to the atmosphere between the steps of forming the first metal and the second and third metals.
JP63287465A 1988-11-14 1988-11-14 Method for manufacturing semiconductor device Expired - Fee Related JP2697796B2 (en)

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Application Number Priority Date Filing Date Title
JP63287465A JP2697796B2 (en) 1988-11-14 1988-11-14 Method for manufacturing semiconductor device

Publications (2)

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JPH02133923A true JPH02133923A (en) 1990-05-23
JP2697796B2 JP2697796B2 (en) 1998-01-14

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5395795A (en) * 1991-04-09 1995-03-07 Samsung Electronics Co., Ltd. Method for fabricating a semiconductor device
JPH07161813A (en) * 1993-12-08 1995-06-23 Nec Corp Method for manufacturing semiconductor device
US6150252A (en) * 1995-05-23 2000-11-21 Texas Instruments Incorporated Multi-stage semiconductor cavity filling process

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS628542A (en) * 1985-07-04 1987-01-16 Toshiba Corp Manufacture of semiconductor device
JPS6242560A (en) * 1985-08-20 1987-02-24 Fujitsu Ltd Electrode for semiconductor device
JPS63125681A (en) * 1986-11-12 1988-05-28 Matsushita Electric Ind Co Ltd Thin film forming device
JPS63157418A (en) * 1986-12-22 1988-06-30 Oki Electric Ind Co Ltd Formation of electrode
JPH025521A (en) * 1988-06-24 1990-01-10 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS628542A (en) * 1985-07-04 1987-01-16 Toshiba Corp Manufacture of semiconductor device
JPS6242560A (en) * 1985-08-20 1987-02-24 Fujitsu Ltd Electrode for semiconductor device
JPS63125681A (en) * 1986-11-12 1988-05-28 Matsushita Electric Ind Co Ltd Thin film forming device
JPS63157418A (en) * 1986-12-22 1988-06-30 Oki Electric Ind Co Ltd Formation of electrode
JPH025521A (en) * 1988-06-24 1990-01-10 Fujitsu Ltd Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5395795A (en) * 1991-04-09 1995-03-07 Samsung Electronics Co., Ltd. Method for fabricating a semiconductor device
JPH07161813A (en) * 1993-12-08 1995-06-23 Nec Corp Method for manufacturing semiconductor device
US6150252A (en) * 1995-05-23 2000-11-21 Texas Instruments Incorporated Multi-stage semiconductor cavity filling process

Also Published As

Publication number Publication date
JP2697796B2 (en) 1998-01-14

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