JPH02136947A - Cash memory having monitor index - Google Patents

Abstract

PURPOSE: To improve the execution performance of the whole system by preventing a cache memory from being interrupted for determining whether data is stored in a cache memory system or not. CONSTITUTION: When a processor 24 is to fetch a data block from a memory, a cache monitor index 46 is checked without interrupting a cache data memory 42 and a cache index 44 by the existence of the data block of a cache data memory 42 and is made use impossible for the processor 24. Therefore, whether data words are stored in the data memory 42 or not can be determined without interposing the processor 24. Thus, the execution performance of the whole system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system having a cache memory that allows a 7°cX setter to quickly access necessary data.

[Conventional technology]

Cache memory is widely used in computers. Cache memory systems include small, fast memories that hold portions of the data stored in a computer's main memory. The data in the cache memory is generally data that the processor is likely to use.

When the processor needs data, it first checks the cache memory to determine if it can read it from the cannon memory instead of reading it from the large, slow main memory.

Kikanso/Yu Memory is the data used by Zoro Sensor.
data or content memory for storing words;
and an index memory for storing addresses for each block of words.

When the processor needs a data word, the main memory address (or part of the address) of the data word is transferred by the Zoro sensor from the cache memory.
being able to obtain the word, i.e. “hit”
Or check the index memory address for a match.

However, in multiprocessor systems, cache memory can sometimes become an impediment to processor operations. When the processors of such a system share a main memory and wish to upgrade or change a data word stored in that memory, the corresponding data word in the memory of each sensor is
The word will have to be changed as well. That is, the data in each cache memory must be correctly reflected in the data in raw memory, and
This is because the processor will use incorrect data and the entire system will lose some of its inertia of operation.

This problem occurs in prior art multi-processor systems in which each cache memory interrupts itself (disables data access from its own processor) when writing data to its main memory. I solved it by asking for this.

[Problem that the invention seeks to solve]

However, in prior art systems, there was no way to check the cache memory when modifying or updating data in main memory without interworking the cache memory.

Obviously, the performance of the processor is reduced if the cache memory is interleaved to check its contents and data access from its own sensor is not available. In a multiprocessor system, each Zoro sensor must wait for its own local cache memory to check for writes from other processors, greatly reducing overall system performance. Furthermore, in typical multi-processor systems, one processor's cache memory cannot store data for use by other processors. This means that each processor typically has 3 files, 2 rows, and a different file in each memory. Because I remember it. As a result, even in most cases where each local cache memory is interwoven to check its contents to see if any data words have been modified by other processors,
The data word it needs is not there. Therefore, each cache memory of each processor is part of the inertia of the system? The basic idea is to check to ensure that the data needed is not present when the cache memory is interoperated for checking.

It is therefore an object of this invention to provide a new and improved cache
The memory system is to provide gold.

Another object of the invention is to provide an improved cache memory system for use in a multi-processor data processing system.

Still another object of the present invention is to provide a multi-processor system in which each processor has a cache memory and data in the cache memory is evicted when modified or updated by other processors. It is to provide.

It is a further object of the present invention to provide a cache memory system that does not require cache memory to be interleaved to determine whether data is stored in the cache memory system.

[Means for Solving the Problems] The present invention has solved the above problems as described below. That is, according to the invention, a data memory stores data words that are also stored in the main memory of the data processing system and stores address bits for each data word stored in the gutter word. The above problem has been solved by providing a cache memory system that includes an index memory and a monitor index memory that also stores the address bits of each data word stored in the data word. The index memory is accessed by the processor associated with its cache memory to determine whether a data word is stored in the rotor memory. The monitor index memory can be accessed without interfering with the processor's use of the cache memory.

In a preferred embodiment of the invention, a multi-grossette
A cache memory system as described above is provided for each processor of the data processing system. When each processor needs to retrieve data from main memory, it provides an address to the index memory of the appropriate cache memory system to determine if the data is also stored in the cache memory system. do. Data in memory processor or main memory? The address of that data, so that when you write it, you can evict it if that data is in another cache memory system? Other cache memory
A monitor index memory for each of the systems is also provided. However, if that data is not in other cache memory systems (this is unlikely, since it is unlikely that data in one cache memory is also in other cache memories), The cache memory and processor proceed without being interwoven.

Each data main memory address includes first and second address portions. Index memory and monitor in 7J memory are each the second address part? It has a memory location that is addressed by the first address portion that it stores.

The comparison memory is connected to the index memory and the monitor index memory, such that the second address portion read from the index memory matches the second address portion of the main memory address provided to the index memory. and the second address portion read from the monitor index memory is
If the data is stored in the cache memory system if it matches the second address part of the main memory address part supplied to the index memory -
Display the information.

It is an advantage of the present invention that each cache memory in a multi-processor system can be checked for the presence of data to be modified or updated by the system's processors without interworking the cache memories. be. The system can maintain its integrity because data written to memory by the processor is evicted from each cache memory.

〔Example〕

FIG. 1 is a multi-processor system 10 of the present invention. System 10 includes multiple processor subsystems 12
(only two of which are shown) and a main memory 14 from which data can be written or read. 7 stem 10 also includes an I10 interface 16 that connects system 10 with human power/output (Ilo) devices such as user terminals, disk memory, and such devices. Data and addresses are transmitted between each mosiel of system 10 by system path 18.

Each processor subsystem 12 has main memory 14
includes a cache memory unit 20 for temporarily storing some of the data stored therein. unit 20
The r-data stored in is selected on the basis of the data most likely to be used by the associated processor subsystem 12.

Each cache memory unit 20 from main memory
The computer programs and other means for selecting data sent to may be conventional.

FIG. 2 shows details of processor subsystem 12.

The processor subsystem 12 includes a processor unit 24, the aforementioned cache memory unit 20, and a 7'Locenosa subsystem 12 in the system path 1.
Pass Driver/Receiver 2 to Interface 8
5.26.

In FIG. 2, system bus 18 consists of a memory data bus 18A and a memory address node 18B. Memory data bus 18A is connected to internal data path 27 by bus driver/receiver 25, and memory address bus 18B is connected to internal address bus 27 by bus driver/receiver 25.
bus 32 and to internal monitor address path 34 by path driver/receiver 26. Processor 24 is connected to data bus 27 to
32f-ta-pinto DI-D32 between pass 27
and 4-no-yari-ti-pino) are transmitted and received from PO to P3.

Processor 24 is connected to address bus 32 to send 26 address bits Al-A26 & 4 parity bits PO-P3 from the processor to address bus 32.

In operation, processor subsystem 12 fetches data and programs from main memory 14 (FIG. 1) via system path 18 while temporarily ignoring cache memory unit 2o. Prosensor 2
4 sends a main memory address to main memory 14 via address bus 32 and memory address bus 18Bk.

(-, then memory data bus 18A and data
The data or program instructions are returned to the addressed memory location via bus 27 to processor 24. After the data has been modified by processor 24, it can be written to main memory at the memory location specified by the address provided by the processor on memory address path 18B. Parity bits PO-P3 are address bits [A1-A24 and data pins DI-[
) 32 to detect bit errors that occur during the transmission of these data.

Cache memory unit 20 (FIG. 2) includes a cache data memory 42, a cache index 44, a cache monitor index 46, and comparison lock circuits 48,50. Cache data memory 42 stores a portion of the data in main memory 14. In the preferred embodiment of FIGS. 4A and 4B, cache data memory 42 includes raw memory 14.
A total of 256 data blocks (each block consisting of 4 words and each word consisting of 4 data bytes) are stored in the cache data memory 42. The data input and output terminals of the cache data memory are generally data that may be fetished by processor 24.
1-D32 and 4 parity bins) PO-P3 are connected to data path 27 for reading and writing. The address input for the cache data memory 42 is Address Pino)A.
1 to A14i is connected to the address path 32 for receiving.

Cache index 44 and cache monitor
Each index 46 stores the address focus for each block of data stored in cache data memory 42. Both the cache index and cache monitor index 46 data inputs are the main memory address bits A15-A26, the valid bits PO, Pl and the two valid bits VQ, Vl.
i is connected to address bus 32 for receiving. Both the cache index and cache monitor index address inputs are used to receive bits from either address path 32 (pintos A3-A14) or monitor address path 34 (bits MA3-MA1.4). Connected. cache index 4
The bits from the data output of 4 are passed from the address path 32 to the compare logic circuit 48 as bits A15-A26, PO
, PI, the bits of data from cache monitor index 46 are sent from monitor address path 34 to comparison logic circuit 50 (PI) MA15.
~MA26. Supplied together with PO and PL. As will be detailed later, the output signal HIT from the comparison circuit 48
The block needed by processor 24 is cached.
Indicates whether data is in memory 42, circuit 5
The zero output signal LMONHIT indicates whether there is a 7J data block in local cache data memory 42 that has been written (updated or modified) to memory by a processor in one of the other processor subsystems 12. indicate.

The actual manner in which cache memory unit 20 (FIG. 2) operates will now be described in conjunction with FIG.

FIG. 3 shows the bits stored in or used in cache index 44 and cache monitor index 46 addresses. In Figure 3, main memory 1
Each data word address for 4 consists of 2,6 bits (Al-A26).

Processor 24 always picks up data blocks from memory using AI 5-A26t (blocks are 4
7-word), one word of the block is fetched, and each of the remaining three words of the block is sequentially sent from main memory 14. AI, A2 is used as a word monitor and is added by the processor as each word of the fetched block is returned from memory. Bit A1 of main memory address
5-A26 define data punctures or segments of main memory. There are 64 memory punctures in main memory 14, defined by address bits AI5-A26, and 256 data blocks, defined by address bits A3-A26 (with 4 data blocks in each puncture). in main memory. Address bits AI5-A26 are cache data memory 42
For each data block stored in cache index 44 (and the corresponding memory location in cache monitor index 46), address bits A3-A14 are stored in cache index 44 (and the corresponding memory location in cache monitor index 46). and cache monitor index 46). Parity bits PO, PI and valid bits VQ
, Vl are stored with each set of address bits AI5-A26 in cache index 44 and cache-monitor index 46. - The parity bit is used to check for parity errors when address bits are read from the cache index and cache-monitor index. The valid bit is written to both indices 44.46 as 0'' when the corresponding data block in cache data memory 42 is accessed, indicating that the data block is no longer valid. Expel.

Cache memory unit 20 operates as a single set associative (direct map) memory, with cache data memory 42 capable of storing a number of data blocks equal to the size of one block of main memory 14. It means that. cache data
A data block stored in memory 42 may be from any one of the memory punctures, but only one data block may be stored from each memory puncture's corresponding data block location. In other words, each memory puncture i4 has a data block (location 1
~4096) When a stored data block is from any one of the memory punctures, only one data block from position 2 of any memory puncture is stored. , and so on.

The cache memory unit 20 of the present invention is characterized by a cache memory unit 20 having a single set of associative memory.
This means that the application is not limited to memory. For example, there can be two data cache memories 42 in each cache memory unit 20, doubling the size of the cache memory.

For each cache data memory 42 there is a separate cache index 44, cache monitor index 46, comparison circuit rumor 8 and comparison circuit 42.
is necessary.

In FIG. 2, when processor 24 wants to fetch a block of data from memory, it enters address path 32 (7).
” supply bits A1-A26 (representing the address of one word of the block).

Address bits A3 to A14i are input to the address of Gannonyu index 44 (memory location it is specified).
Bi□ζ (A15 to A26) received and stored in the memory location specified by the cache index is supplied to the output (increase) overnight. Cache in f:
<The bit in the address data output is address path 3
When bits A15-A26 of 2 are matched, the data block requested by the processor is placed in cache-data memory 42, and comparison logic circuit 48 provides an enable signal HITi at its output. The cache data memory 42 is enabled by the processor 24 in response to the signal HITK and addresses bits A1-A1.
4. Provides data to the memory location defined by 4.

If cache data memory 42 does not have the data block requested by the processor, it fetches the data from main memory. Processor 24 also retrieves cache data from main memory by supplying an address path 32 to main memory 14 via memory address path 18Bt.
Data blocks can be transferred to memory 42 (as expected). The data block is returned to cache data memory 42 via data path 27 and stored along with 41 retention bits in the memory location specified by address bits A1-A14 from address path 32. be done.

At the same time, the address bits used to fetch data blocks are cached for data inputs (bits A15-A26) and address inputs (bits A3-A14).
is sent to index 44 along with the /'' property bit and valid bit.

The operations of processor 24, cache data memory 24 and cache index 44 described above are conventional and can be found in computers with character memory.

The cache monitor index 46 of this invention is
The existence of a data block in cache data memory 42 is checked without the cache data memory and cache index Q444t' being interwoven, providing that they are unavailable to processor 24. cache monitor index 46
is the same bit as cache index 44 (A15
~A26. PO, PI, VO, Vl)' and these bits are stored in the cache index 44.
are stored in the same way as they are stored in the same way.

Monitor address path 34 indicates that any processor in SynuTem 10 sends memory address 4.1. The same bit is set to the monitor address node 34 of each processor subsystem 12 whenever the Al-A 26 is placed on the MAI.
~MA 26, and so on, is connected to memory address path 18B by path driver/receiver 26.

Bits MA3-MA14 are provided to the address input of cache monitor index 46,
The bits in the data output of monitor index 46 are bits MA15-MA26, pQ, p1
is compared in comparison logic circuit 50 to determine whether the data to be written to memory is in local cap data memory 42.

Data written to memory is cache memory 4
2, the valid bits (v□, vt) for the data block in both cache index 44 and cache-monitor index 46 are both marked (written as NO'') and the data block is evicted. , local processor 24 does not use the data.

Figures 4A and 4B show the cache memory unit 20.
Show details. Before proceeding to the discussion of Figures 4A and 48, note that signals with 6'°' at the end of the signal display are active at 0' and signals without are active at 1''.

In FIG. 4A, address input A of cache index 44 is connected to address input 32 and monitor address input A is connected to address input 32 by a multiplexer (MUX).
It is connected to path 34. Similarly, Charatsuyu Monitor
Index 46 is multiplexer (MUX) 82
K is connected to monitor address nozzle 34 and to address path 32.

A processor associated with cache memory unit 20 uses address path 3 for fetching from memory.
2, address bits A3-A
14 is address input A of cache index 44
is supplied by MUX 80. address path 3
In addition to the bits (PO, PI) of 2, the other bits (A15-A26) of the memory address are compared with the bits of the data output DO of the cache index 44 in the comparison logic circuit 48. .

If a processor other than the one associated with cache memory unit 20 supplies an address to the memory address path for a 7 etch from memory, the address is sent to the monitor address path 340 bits MAI.
I'll be 26. l1iliUX82 sets bit MA3 to address input A of cache monitor index 46.
~MA 14 i send. Memory address path 2
Other memory address bits (MA l 5 to MA26) sent along with the 7 mother property bits (PO, PI)
) is compared with the bits of data output DO of cache monitor index 46 in comparison logic circuit 50.

When a HIT'' occurs in cache monitor index 46 indicating a memory write and store to cache data memory 42 by another processor, MUX_SO sets bit MA3 to address input A of cache index 44. ~MA 14k
Send. At the same time, the data input DI of cache index 44 and cache monitor index 46
The two valid bits Vo, Vl in cache in 7J Nox 4 are set to 0'' by processor 24
4 and the signals at the write enable inputs of cache monitor index 46 ITE and MIWRI
Written to cache index 44 and Karatsuyu monitor index 46 under the control of the TE.

MUX s o is its selection input SEL (7) Signal MO
bits A3-A14 or bit M by NHITwI
It is controlled to pass through any one of A3 to MA14.

yDNHITW' is provided by the processor 24 and "HI
It is active (at ``0'') only when T'' occurs in cache monitor index 46.

When a data block is fetched by the processor and stored in cache data memory 42, address bits A3-A14 of the memory address from address path 32 are input to cache and monitor index 44 by MUX 80 and MUX 82. .46 address input. At the same time, when bits A15-A26, PO, and PI are supplied to the data inputs of cache index 44 and cache monitor index 46, they are stored respectively, and the data blocks corresponding to each memory address are stored as cache data. - fed to data input DI of memory 42 and stored therein; Cache monitor index 46 is enabled and data?? by signal MIWRITE on its write enable input. Remember. MUX82 is the selection input SE
bit A3 by the signal biONWRI TE at
-A14 or bits MA3 to MA14.

MONWRITE is provided by processor 24;
Data blocks are cached data memory 42
is active (at “1”) only when it is to be written to.
Vl) also memory address bits AI5 to A26
．． Written to the cache monitor index (as 1”) along with PO and PI.

Parity check circuit 86 of FIG. 4A checks the parity of each address applied to internal address path 32. i? If a quality error is found, circuit 86
The output signal ADRPARERR becomes active (1'').

The comparison logic circuit 48 of FIG. 4B is a dual comparison logic circuit 90.
, a noise check circuit 92, and two latches 9.
4,96 and and date 98°100.102. The outputs of comparator 90 are or wired together and the resulting signal is provided to latch 94. The output of latch 94 is provided to AND gate 98. Parity check circuit 92 checks the parity of the memory address bits of the output of cache index 44;
Its output is provided to launch 96. The output of latch 96 is provided to both AND gate 98 and AND gate 100. A signal CA that is active (l”) only when the cache memory is available for supplying data.
CHE ENABLE and processo? 24 is 2 sex (
The signal FPREAD is active (11”) only when reading (reading) or writing (storing) data.
WRT are both supplied to AND gate 102.

The output of AND gate 102 is provided as a second input to AND gate 100. and dirt 1
The 00 output signal IPARERR is provided to the processor 24 and becomes active ("1") only when a /4'ity error is detected in a bit from the cache index 44 during a fetch or store.

The output of AND gate 98 provides a signal "HIT" which is active ("1") only when the memory address of address path 32 matches the address of cache index 44.

Signal ADRPARE from parity check circuit 86
If RR is active, is there an error in the memory address? and the signal CACHEEN
When ABLE' is active, it indicates that the cache data memory 42 is unable to supply data;
When the output of the error check circuit 92 (by the latch 96) is active, the output of the cache index 44 indicates an error, and the output signal HIT of the AND key 98 is active. active (and the inverse signal MISS becomes active), and the processor 24 uses the cache data memory 42
address data block is not available.

Comparison logic 50 in FIG. 4B includes Puer comparator 106;
/4'ity check circuit 108, and dirt 1
10, 112, 114, lunch 116, 118 included.

Comparator 106 selects bit M of monitor address path 34.
Compare A15-MA26, PO, P1 with the output of cache monitor index 46. The outputs of comparators 106 are wire-ORed together and
- 110 manpower is supplied. and gate 11
The other input of 0 is the cache-monitor index 46
receives a signal MONENABIJ' which is active (0'') only when the cache monitor index 46 is enabled.
ABLE' is "0"), AND gate 11O passes the match signal from comparator 106 as signal LMONHIT and the data stored by processor 24 for local cache memory unit 20 is stored in the cache memory of FIG. 4B. Indicates that it is in data memory 42.

The integrity check circuit 82 is a cache monitor.
It checks the A' property of the bit from the output of index 46 and provides its output to all launches 116 and AND gate 112. and r-)1
Another input of 12 is a signal MONE which is active when cache monitor index 46 is enabled.
NABLE i Receive. The output of AND gate 112 is connected to the output of AND gate 110 (signal LMONHI
T) or wired and fed to latch 118.

As a result, when cache monitor index 46 is enabled, signal LMONHIT (and its inverse signal LMONHIT') is either a match at comparator 106 or a parity signal as indicated by the output of parity check circuit 108.・If either error occurs, latch 1
18 outputs.

The output of parity check circuit 108 is also provided to latch 116 and AND gate 114.

The other input to AND DART 114 is the signal MONE.
The signal MONI PARERR at the output of the ABLE ant"-?-1-104 is active only if there is an error in the cache monitor index 46 and the cache monitor index is enabled. Active (1”). Signal MONI PARER
R is supplied to the processor 24 and cache monitor
The index 46 indicates that an error condition has occurred.

The two inputs of both comparators 90, 106 of FIG.
provides a means to compare the valid bits from the . clearly,
If the valid bit does not match the active signal, the addressed data is previously evicted and read from cache data memory 42.
6 is California, 5anta C1ara's 'Fujitsu Microelectronics
It can be purchased from , Inc.

All other parts in Figures 4A and 4B are Ar1zon.
a. Phoenix Motorola Sem1c
It can be purchased from onductor Products, Inc. Their part numbers are shown in Table I below.

A cache index and a cache monitor index according to the present invention described below.
A memory can be examined and determined whether there is data in it without interworking its processors.

Table I Component Cache data memory 42 cash index 44 Cache monitor index 46MUX 80 MUX 82 Security check circuit 86 Comparator 90 Noise check circuit 92 latch 94 Lunch 96 and gate 98 and gate 100 and gate 102 Comparator 106 /Dirity check circuit 108 andrto110 and gate 112 and gate 114 latch 116 latch 118 part number 0H158 oH158 0H160 0H166 0H160 0H175 +0H175 0H209 0H104 1QHI 04 0H166 0H160 0H209 0H104 0H104 0H130 0H130

[Brief explanation of the drawing]

1 is a simplified block diagram of the multiprocessor data processing system of the present invention; FIG. 2 is a block diagram of one of the prosensor subsystems of FIG. 1; FIG. 3 is a block diagram of one of the processor subsystems of FIG. Diagrams of the bits stored and used in cache index and cache monitor index addresses, FIGS. 4A and 4B, are block diagrams of the cache memory unit seen in FIGS. 1 and 2. It is. In the figure, 10...multiprocessor, system, 12...
・Processor subsystem, 14...Main memory 1
6...I10 interface, 18...system
Has, 20...cache memory unit. Applicant's agent Isao Saito FIG, 1 FIG, 3

Claims (1)

[Claims] (1) In a data processing system having a processor and a main memory for storing data words used by the processor, the data memory for storing at least a portion of the data words also stored in the main memory; , an index register addressed by the processor that stores an address for each data word stored in the data memory and determines whether a data word for use by the processor is stored in the data memory; , storing an address for each data word stored in the data memory and being addressed independently of the processor to determine whether to store the data word in the data memory without involving the processor; A cache memory system that includes a monitor index memory.