JPH02138734A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remove an interlayer leak by a method wherein an insulative film is etched until the surface of a conductive film appears and a wiring material is deposited on the whole surface of a substrate to obtain a contact with the conductive film. CONSTITUTION:A silicon oxide film 22, gates consisting of a poly silicon film 23, a first CVD silicon oxide film 24, an n<+> diffused layer 25 which is used as source and drain regions, and a MOSFET having a second CVD silicon oxide film 26 are formed on a silicon substrate 21. Moreover, after a pattern is formed of a photoresist 30, the film 22 in a contact hole part 34 is etched and after the resist 30 is removed, a silicon epitaxial growth layer 35 is selectively grown only in the hole 34, under which the layer 25 is exposed, to fill the step differences of the hole 34. Then, a third CVD silicon oxide film 36 and a borophosphate glass film 29 are deposited, a heat treatment is performed at the softening point or higher of the film 29 and the film 29 is reflowed and flattened. Then, the film 29 is etched back until the surface of the layer 35 appears on the surface and an Al film 37 is deposited as wiring material.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.

BACKGROUND OF THE INVENTION In recent years, with the miniaturization of devices, self-line contact technology has become indispensable as a contact formation technology in the submicron region.

The process of forming a self-line contact in a conventional MOS (MOS) transistor formation region will be described with reference to FIG.

First, as shown in Figure 3), on the silicon substrate 1,
Silicon oxide film 2. A gate made of polysilicon film 3,
10VD silicon oxide film 4 separating the gate and wiring
, an n+ diffusion layer 5 which becomes a source region or a drain region,
20th VD silicon oxide film 6 forming sidewalls
A MOS transistor is formed.

Next, as shown in FIG. 3(b), C
VD silicon nitride film? , an n+ polysilicon film 8 and a poron phosphorus glass film 9, which will serve as an insulator film, are deposited over the entire surface.

Next, as shown in FIG. 3C, after forming a pattern using photoresist 10, boron phosphorus glass film 9 is etched using n+ polysilicon film 8 as an etching stopper.

Next, as shown in FIG. 3(cl)K, the n+ polysilicon film 8 is etched using the CVD silicon nitride film 7 as an etching stopper.

Next, as shown in FIG. 3(e), heat treatment is performed in an oxidizing atmosphere to oxidize the n+ polysilicon film 8 into a polysilicon oxide film 11.
Since there is a CVD silicon nitride film 7 which is an oxidation prevention film under the polysilicon film 3 and the silicon substrate 1, the polysilicon film 3 and the silicon substrate 1 are not oxidized. Also, at this time, since the poron phosphorus glass film 9 is reflowed, the interlayer insulating film is flattened.

As shown in FIG. 3(f), the CVD silicon nitride film 7, which is an oxidation prevention film, and the silicon oxide film 2, which is a protective oxide film in the contact formation region, are etched. Thereafter, as shown in FIG. 3(q), an n+ polysilicon film 12 and an AI film 13, which are wiring materials, are deposited.

Problems to be Solved by the Invention However, the above configuration has a problem in that various interlayer leaks occur and the yield of semiconductor devices is low. The reason will be explained below.

First, since the silicon nitride film is used as an oxidation prevention film between the polysilicon film and the silicon substrate during the flow of the boron phosphorus glass film, the thickness of the silicon nitride film cannot be made very thin. Therefore, various leaks occur due to stress on the silicon nitride film.

Second, when etching a silicon nitride film and a silicon oxide film, if the amount of overetching is large, the underlying n+
Since the diffusion layer is dug down and becomes shallow, leakage occurs between the silicon substrate and the n+ polysilicon film that is the wiring material. Furthermore, at this time, the first CVD on the underlying gate
No. 20 forming the silicon oxide film and sidewall
The VD silicon oxide film is dug down and becomes thinner, and leakage occurs between the gate polysilicon film and the n-polysilicon film that is the wiring material.

The present invention was attempted in view of the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the above-mentioned interlayer leakage.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention includes a step of depositing a conductive film in a contact hole on a semiconductor substrate without using a silicon nitride film, and a step of depositing an insulating film on the entire surface of the semiconductor substrate. a step of etching the insulating film until the surface of the conductive film is exposed; and a step of making contact with the conductive film by depositing a wiring material over the entire surface of the semiconductor substrate. It is something that

Function: With the above-described structure, the present invention does not use a silicon nitride film, so that various leaks due to stress do not occur. Furthermore, since planarization is performed after filling the contact hole with a conductive film, the insulating film covering the n+ diffusion layer and the gate is not dug down, so interlayer leakage can be eliminated.

Embodiment (Embodiment 1) FIG. 1 is a process cross-sectional view of a method for forming a self-line contact in a MOS transistor formation region according to a first embodiment of the present invention. A first embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 1(a), a silicon oxide film 22 is formed on a silicon substrate 21 using a well-known technique. A gate made of a polysilicon film 23, a tenth layer separating the gate and wiring.
A VD silicon oxide film 24, an n+ diffusion layer 26 which becomes a drain region or a drain region, and a second layer which forms a sidewall.
A MOS transistor having a 0VD oxide film 26 is formed. In this embodiment, the gate spacing of the phosphor-contacted MOS transistors is approximately 0.571 m, and the depth of the n+ diffusion layer 26 is approximately 0.
．． It is 2 μm.

Next, as shown in FIG. 2(b)K, after forming a pattern using photoresist 30, the silicon oxide film 22 in the contact hole 34 portion is etched.

Next, after removing the photoresist 30, as shown in FIG.
is grown to fill the level difference in the contact hole 34. In this embodiment, the aspect ratio of the contact hole 34 portion is approximately 1.

Next, as shown in FIG. 1(d), a 30th VD silicon oxide film 36 and a holon phosphorus glass film 29 are deposited.

As shown in Figure 1 (,), boron phosphorus glass 29
The boron phosphorus glass film 29 is reflowed and planarized by heat treatment in a nitrogen gas atmosphere at a temperature equal to or higher than its softening point. In this embodiment, the concentration of the boron phosphorus glass film 29 is 10. ○at% B2O3゜6.5at%
Heat treatment is performed using p2o5 in a nitrogen gas atmosphere at 900'C. At this time, in order to prevent impurities from diffusing from the boron phosphorus glass film 29 to the underlying layer, the 30th VD silicon oxide film 36 is deposited to a thickness sufficient to prevent impurity diffusion, for example, about 50 nm. .

Next, as shown in FIG. 3(f), the boron phosphorus glass film 29 is grown until the silicon epitaxial growth layer 36 appears on the surface.
to have sex back. At this time, if the underlying first CvD silicon oxide film 24 and 20th VD silicon oxide film 26 are etched and the film thickness becomes thinner, leakage is likely to occur between the gate polysilicon film 23 and the wiring. Therefore, the silicon epitaxial growth layer 35 is grown to a position several tens of nanometers higher than the 10th vD silicon oxide film.

Finally, as shown in FIG. 1 (CF) K, an AI film 37 is deposited as a wiring material.

As described above, according to the first embodiment, by filling the contact hole with a silicon film, there is no need to use the n+ polysilicon film 8 as an etching stopper as in the conventional example, and the n+ polysilicon film 8 can be used in a post-process. There is no need for oxidation in an oxidizing atmosphere, so the silicon nitride film 7 as an oxidation prevention film is no longer necessary. Therefore, various leaks due to stress do not occur.

In the first embodiment, the third CVD silicon oxide film 36 is used as an impurity diffusion prevention film when heat-treating the boron phosphorus glass film 29, but the same effect can be obtained by using a sputtered silicon oxide film.

(Embodiment 2) FIG. 2 is a process cross-sectional view of a method for forming a self-line contact in a MOS transistor formation region according to a second embodiment of the present invention. A second embodiment of the present invention will be described below with reference to FIG.

Since the steps in FIGS. 2(a) to 2(C) are the same as those in FIGS. 1(d) to (c), the detailed explanation will be omitted by assigning the same numbers to each component.

Next, as shown in FIG. 2(d), a 40th VD silicon oxide film 40 is deposited and a photoresist 41 is applied.

Then, as shown in FIG. 2(e), the photoresist 41 and the 40th VD silicon oxide film 40 are etched under conditions that allow the photoresist 41 and the 40th VD silicon oxide film 4o to be etched at the same rate until the surface of the silicon epitaxial growth layer 36 appears. After backing up, an AI film 42 is deposited as a wiring material as shown in FIG. 2(f).

As described above, in the second embodiment, unlike the first embodiment, flattening by heat treatment is not performed, so the insulating film that fills the steps other than the contact holes does not need to be limited to boron phosphorus glass. .

Further, it is not necessary to deposit the 30th VD silicon oxide film as an impurity diffusion prevention film.

Therefore, when flattening by heat treatment is easy, the method of the first embodiment can be used, and when it is difficult, the method of the second embodiment can be used.

In the second embodiment, the step of the contact hole was filled with a silicon epitaxial growth layer, but the same effect can be obtained by selectively depositing tungsten, and any other conductive film can be used. Needless to say, it's a good thing.

Effects of the Invention As is clear from the above explanation, since the present invention does not use a nitride film as an oxidation prevention film during planarization accompanying the formation of self-line contacts, various leaks due to stress do not occur. Furthermore, since planarization is performed after filling the contact hole with a conductive film, the insulating film forming the n+ diffusion layer and the gate is not dug down, and interlayer leakage can be eliminated. Therefore, the yield rate of semiconductor devices can be improved.

[Brief explanation of the drawing]

1 and 2 are process cross-sectional views of a method for forming a self-line contact according to a first embodiment and a second embodiment of the present invention, respectively, and FIG. 3 is a process sectional view of a conventional method for forming a self-seven line contact. FIG. 21... Silicon base &, 22... Silicon oxide film, 23... Polysilicon film, 24...
...First CvD silicon oxide film, 25...
・n+ diffusion layer, 26... 20th VD silicon oxide film, 29... boron phosphorus glass film, 30.41.
... Photoresist 7), 34 ... Contact hole, 36 ... Silicon epitaxial growth layer, 36 ... 30th VD silicon oxide film, 37
, 42=----Al fll, , 4 o-------
4th CV D Silicon oxide film Name of agent Patent attorney Shigetaka Awano and one other figure? 4.JcVD silicon oxide film casting final diagram

Claims (2)

[Claims] (1) a step of depositing a conductive film in a contact hole on a semiconductor substrate; a step of depositing an insulating film over the entire surface of the semiconductor substrate; a step of causing the insulating film to flow by heat treatment; A method for manufacturing a semiconductor device, comprising: etching a film until the surface of the conductive film is exposed; and depositing a wiring material over the entire surface of the semiconductor substrate to make contact with the conductive film. (2) a step of depositing a conductive film on the contact hole on the semiconductor substrate; a step of applying a resist to the entire surface of the semiconductor substrate; and a step of depositing the conductive film on the contact hole on the semiconductor substrate, and depositing the insulating film and the resist at the same speed on the surface of the conductive film. A method for manufacturing a semiconductor device comprising the steps of: etching until the conductive film is exposed; and depositing a wiring material over the entire surface of the semiconductor substrate to make contact with the conductive film.