JPH0213969B2 - - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention is used in a digital communication system using a multi-value amplitude modulation signal, and a multi-value signal of 2 ^M values is input.
This invention relates to a multilevel signal identification circuit that identifies which of the ^2M values a signal belongs to.

``Prior Art'' In order to correctly identify and reproduce a multi-value amplitude signal in a multi-value amplitude modulation system, the input level to the identification circuit must always be accurately maintained within a constant range. For this reason, conventionally, an A/D converter is used as an identification circuit, and the output signal is fed back to a DC amplifier inserted before the A/D converter, thereby keeping the input signal amplitude and DC voltage offset optimal. A configuration has been proposed (see Japanese Patent Application No. 58-18149 (Japanese Unexamined Patent Publication No. 59-144218) "Multi-level discriminator"). The configuration of this conventional discriminator circuit is shown in FIG. A multi-value amplitude signal of 2 ^M values (M is an integer of 2 or more) from the input terminal 11 is amplified by the DC amplifier 12, and the output of the DC amplifier 12 is converted into an analog signal in synchronization with the clock from the clock input terminal 13. It is converted into a digital signal by a digital (A/D) converter 14.The A/D converter 14 has M+1
This is a bit output converter, which identifies the input signal into 2 ^M+1 values and converts it into a digital signal 15 of M+1 bits. The control circuit 16 receives the digital signal 15
A feedback signal 17 for controlling the DC voltage offset of the DC amplifier 12 and a feedback signal 18 for controlling the gain are outputted by a combination of one bit or a plurality of bits output. The feedback signals 17 and 18 are smoothed through low-pass filters 21 and 22, respectively, and supplied to the DC amplifier 12 as control signals 23 and 24. These control signals 23 and 24 automatically adjust the offset and gain of the DC amplifier 12, respectively. As a result, the input level of the A/D converter 14 is always kept optimal.

FIG. 2 shows the relationship between the input signal level and the output signal sequence of the A/D converter 14 when ^{a 2 3} =8-value signal is input. From FIG. 2, the identification level of the fourth bit from the highest is equal to the signal point (level) of the 8-value signal. Therefore, the output result of the fourth most significant bit indicates the direction of error in the input signal. As shown in FIG. 2, if the amplitude and offset of the input signal are ideal, the output of the fourth bit will be "0" or "1" with a probability of 50%. Therefore, offset feedback control using the output of the 4th bit becomes stable.

On the other hand, due to some factor, the input signal has a minimum inter-signal voltage value (voltage between adjacent levels in multilevel levels) d
When offset positively or negatively by an integer multiple of
Since the output of the fourth bit is "0" or "1" with a probability of 50%, there are cases where the feedback control signal becomes stable. This state is called a pseudo-retraction state. This pseudo-retraction state causes identification errors, and once this state occurs, an equilibrium state is maintained, so there is a problem that identification errors continue to occur. An example of a pseudo-retracted state is shown in FIG. In FIG. 3, the left side during pseudo-retraction shows the state of retraction to a level d higher than normal retraction, and the right side shows the state of retraction to a level d lower.

A multi-value discrimination circuit with small fixed deterioration for such a pseudo-retraction state is proposed in Japanese Patent Application No. 59-37106
-180259 Publication) ``Multi-value identification circuit''. This is the case when the A/D falls into a pseudo-retraction.
The control loop includes a circuit that utilizes the deviation of the mark rate of the output signal of the converter to switch the feedback signal for controlling the offset of the DC amplifier from the error signal to the bit identification signal. In this configuration, once a pseudo pull-in occurs, it is detected and the normal state is restored, so there is a drawback that the line is disconnected from the pseudo pull-in until the normal state is restored.

The purpose of this invention is to avoid falling into pseudo-retraction,
It is an object of the present invention to provide a multilevel signal discrimination circuit that can always keep the DC offset of an input signal optimal.

``Means for Solving the Problems'' According to the present invention, an A/D converter for identifying a multi-value input signal of ^2M values can be used as an A/D converter for identifying a multi-value input signal of 2M values.
is an integer of 2 or more) output is used, and the lower K bits (K = N
-M) is input to a determination circuit, and it is determined whether the DC drift of the multi-level input signal is greater than or equal to a predetermined value. When an analog quantity output corresponding to at least 1 bit in the M bit output is output from the feedback signal generation circuit and is set to be less than a predetermined value,
Outputs an analog conversion signal of at least the upper 1 bit (M+1st bit from the higher order of the A/D converter) of the lower K bits, and the output of the feedback signal generation circuit is supplied to the low-pass filter. The output of the low-pass filter is supplied as a control signal to a DC amplifier inserted before the A/D converter.
The DC offset of the multivalued input signal is controlled to reduce the DC drift.

"Example" Examples of the present invention will be described below. FIG. 4 shows a case where the present invention is applied to M=3, that is, 2 ³ =8-value input signal. The 8-value input signal is input to the input terminal 11, passes through the DC amplifier 12, and is then sent to the A/D converter 13.
is input. The DC amplifier 12 is capable of controlling the DC offset of a multi-value input signal in the same way as the one shown in FIG. A control signal 23 for controlling the DC voltage offset is supplied to the inverting input as a DC reference signal. The upper 3 bits output B ₁ B ₂ B ₃ of the N-bit A/D conversion output output from the A/D converter 14 in synchronization with the clock from the terminal 13 are used as identification outputs. The upper three bits B ₁ B ₂ B ₃ satisfy the relationship shown in FIG. 2 depending on the amplitude value of the binary input signal. Furthermore, bit _B5 in the output of the A/D converter 14
Regarding the following input/output relationships, as shown in FIG. 2, the identification area is divided into halves as it progresses to lower bits. When an 8 (=2 ³ ) value signal is input, the output _B4 of the fourth bit from the higher order is an error signal indicating the polarity of the DC drift of the multi-value input signal.

Lower K=N-M in the output of the A/D converter 14
The bit outputs B ₄ , B ₅ ...B _N are input to the determination circuit 26 to detect the polarity and amount of DC drift, and it is determined whether the DC drift has exceeded a predetermined value. The determination circuit 26 outputs "+1" when the drift is above the reference value, and outputs "0" when the drift is below the reference value.

When the determination circuit 26 determines that the value is equal to or higher than the reference value, at least one of the identification signals B ₁ , B ₂ , and B ₃ is detected by its output.
The addition circuit 27 adds the error signal B4 and the error signal _B4 . In this example, when the output signal of the determination circuit 26 is +1, the analog switch 38 is turned on and the output _B1 of the first high-order bit is supplied to the adder circuit 27, and the output and the error signal _B4 are sent to the adder circuit. The signals are added in an analog manner via addition resistors 31 and 32 in 27. The output of the adder circuit 27 is smoothed through a low-pass filter 21 for integration, and then supplied to the DC amplifier 12 as a control signal 23 to control the DC offset of the multi-level input signal and to reduce DC drift. be made into

In the above configuration, when the DC drift of the multi-level input signal is less than the reference value, the switch 38 is off, so the signal supplied to the filter 21 is only the error signal _B4 , and as explained in FIG. The DC offset is controlled so that the probability that the error signal _B4 becomes "1" or "0" becomes 50%. When the DC offset of the multi-value input signal exceeds the reference value, the switch 38 is turned on and the output _B1 of the first higher bit is supplied to the adder circuit 27, so that the signal supplied to the filter 21 has no error. This is a linear addition of the signal _B4 and the first bit output _B1 .

When the multi-value input signal receives a positive drift, the probability that the outputs B ₁ , B ₂ , B ₃ of the upper M=3 bits all generate "1" increases, and the filter 21
The control signal 23 at the output of the DC amplifier 1 increases more quickly than the error signal _B4 alone, so that the output of the DC amplifier 1
The offset of 2 is controlled to the negative side, and the level of the multilevel input signal is normalized. On the other hand, when the multi-level input signal undergoes a negative drift, the probability that the outputs B ₁ , B ₂ , B ₃ of the upper M=3 bits all generate "0" increases, and only the error signal B ₄ The control voltage 23 increases to the negative side more quickly than in the case of
The offset of 2 is controlled to the positive side, and the level of the multilevel input signal is normalized. However, A/D converter 1
4 outputs +V (volts) at logic "1" and -V (volts) at logic "0".

In this way, by adjusting the magnitude of the offset control signal 23 itself using the lower bit output of the A/D converter 14, a highly accurate multi-value discriminating circuit can be constructed without falling into pseudo pull-in.
Although not shown in FIG. 4, gain control is also performed on the DC amplifier 12 in the same manner as described with respect to FIG. In FIG. 4, adder circuit 27 and analog switch 38 constitute a feedback signal generating circuit 43 that generates feedback signal 17 to low-pass filter 21. In FIG.

The reference value of the DC drift amount used in the determination circuit 26 is the minimum inter-signal voltage value in the multi-value input signal.
, it can take any value within ±d/2, but
Here, it is assumed to be ±d/4. In this case, the 8-value input signal point and the lower 5 = 8-3 (K = N-M)
The relationship between bit error signals B ₄ , B ₅ , B ₆ , B ₇ and B ₈ is shown in FIG. The fourth bit _B4 indicates the direction of the drift, and the fifth to eighth bits _B5 to _B8 indicate the magnitude of the drift.

The determination circuit 26 is configured as shown in FIG. 6, for example. That is, 5-bit comparators 33 and 34 are used, and B ₄ to _{B 8} in the output of the A/D converter 14 are used.
and reference value +d/4 (=10111), -d/4 (=01000)
It is determined whether the drift amount is within ±d/4. When a DC drift of +d/4 occurs in the multi-value input signal, the error outputs B ₄ , B ₅ , B ₆ , B ₇ , and B ₈ become “10111” in that order, as shown in FIG.
becomes. Therefore, the error output of the 5-bit comparator 33 matches the reference value "10111", and the comparator 33 outputs "1", thereby determining that the DC drift of the multi-value input signal exceeds +d/4. Ru.

Similarly, the error outputs B ₄ , B ₅ , B ₆ , B ₇ , and B ₈ which have a DC drift of −d/4 in the multi-value input signal become “01000” in that order, and the 5-bit comparator 34
The error output matches the reference value "01000" and "1" is output from the comparator 34, thereby determining that the DC drift of the multi-value input signal exceeds -d/4.

The outputs of these comparators 33 and 34 are passed through an OR circuit 35 and are outputted from the determination circuit 26. Therefore, the output of the determination circuit 26 is "0" when the DC drift of the multi-value input signal is within ±d/4, and "1" when it exceeds ±d/4. The relationship between the DC drift and each output of the comparators 33, 34 and the determination circuit 26 is shown in FIG.

In the example shown in FIG. 6, all of the identification signals B ₁ , B ₂ , and B ₃ are added in an analog adder circuit 37, and the output is supplied to the adder circuit 27 through an analog switch 38, and the analog 38 is used as the judgment output of the judgment circuit 26. When the output of the judgment circuit 26 is "1", the switch 38 is turned on, and when the output is "0", the switch 38 is turned on.
This is the case when 8 is turned off. In this way the identification signal
By using all of B ₁ , B ₂ , and B ₃ , the DC offset of the multilevel input signal can be rapidly reduced to below the reference value (±d/4).

Generally, the multi-value input signal is 2 ^M values, A/D converter 14
When is an N-bit output, the determination circuit 26 can be constructed in the same manner as shown in FIG. 6 using K (=NM)-bit comparators 33 and 34. Although the reference value of the amount of offset can be changed according to the design, it is possible to deal with this by simply changing the reference values of the comparators 33 and 34.

As understood from FIG. 5, the A/D converter 1
The lower K bits in the output of 4 (B ₄ ~
B ₈ ) changes depending on the magnitude of DC drift. By using these lower bit feedback signals, control according to the magnitude of DC drift becomes possible. For example, as shown in FIG.
The error signal B _M+1 to B _N of the lower K bits of 4 is D/A.
A converter 41 converts it into an analog signal. This error signal B _M+1 to B _N (in Fig. 5, the 4th bit B ₄ to the 8th bit
Bit B ₈ ) corresponds to the DC drift amount of the multi-level input signal. For example, in Figure 5, the amount of DC drift is +
When the DC drift amount is -d/2, the fourth to eighth bits are all "1", and when the DC drift amount is -d/2, they are all "0". From this, the D/A converter 41
The output analog voltage value of is a voltage proportional to the DC drift amount of the multi-value input signal. The judgment circuit 26 controls the analog switch 38 to supply the output of the D/A converter 41 to the low-pass filter 21 if the DC drift is less than ±d/4, and if the drift is more than ±d/4 The output of the adder circuit 37 is supplied to the low-pass filter 21. D/A converter 41
When the output of is being supplied to the low pass filter 21, if the DC drift amount is large, the control signal 2
3 increases, and when the DC drift amount is small, the control signal 23 decreases, so that good control characteristics can be obtained. DC drift of multi-value input signal is ±
When d/4 is exceeded, the output of the determination circuit 26 becomes "1", the switch 38 is switched, the output of the adder circuit 37 is selected, and feedback control is performed.

As shown in FIG. 8, when the drift of the multi-level input signal exceeds ±d/4, the output of the determination circuit 26 turns on the switch 38 and adds the output of the adder circuit 37 and the output of the D/A converter 41. The circuit 27 adds the sum and supplies it to the filter 21, so that the DC drift is ±
If it is less than d/4, the switch 38 may be turned off and only the output of the D/A converter 41 may be supplied to the filter 21. In this way, the DC drift is ±d/
When the number exceeds 4, by adding the first to M bit outputs (identification signals) _B1 to _BM as control signals, a highly accurate multi-value discriminator without pseudo-inclusion can be constructed. Note that the D/A converter 4
1 is supplied to the adder circuit 27, and the resistance value of the resistor 42 is selected to determine the addition ratio between the output of the D/A converter 41 and the output of the switch 38.

In the configurations of FIGS. 7 and 8 as well, at least one bit among the upper bits B ₁ to _BM may be supplied to the switch 38 when the DC drift is greater than a predetermined value.
Further, in FIG. 4, the supply of the error signal _B4 may be stopped when the DC drift is equal to or greater than a predetermined value.

"Effects of the Invention" As described above, according to the multilevel signal discrimination circuit of the present invention, by correctly controlling the DC offset of the input signal of the A/D converter 14, the threshold value of the discrimination circuit can always be optimized. It is possible to maintain
Further, even when the number of multivalues increases, the same circuit configuration is sufficient, and in this case, the configuration becomes even more effective. As a result, it becomes possible to configure a highly accurate multilevel signal identification circuit in multilevel modulation methods such as 64QAM and 256QAM.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional feedback type multi-value discrimination circuit, and FIG.
Figure 3 shows the relationship between input and output when identified by
The figure shows the relationship between the signal point position, the first bit _B1 of the upper output, and the error signal _B4 in the normal pull-in state and pseudo pull-in state in an 8-value input signal,
Fig. 4 shows an embodiment in which the present invention is applied to an 8-value input signal, and Fig. 5 shows a multi-value signal input and an error signal.
A diagram showing the relationship between B ₄ to _{B 8} and each output of the comparators 33, 34 and the determination circuit 26, FIG. 6 is for an 8-value input signal and 8-bit output A/D converter 16, FIG. 7 and FIG. 8 are diagrams showing an example of the configuration of the determination circuit 26 when d is set to ±d/4 (d is the minimum signal-to-signal voltage value), and FIGS. 7 and 8 are diagrams showing other embodiments of the present invention, respectively. . 11...Multi-level signal input terminal, 12...DC amplifier, 13...Clock input terminal, 14...A/D
Converter, 21... Low pass filter, 26... Judgment circuit, 27... Analog addition circuit, 33, 34
... Comparator, 37 ... Analog addition circuit,
38...Analog switch, 43...Feedback signal generation circuit.

[Claims]

1 The first one that generates a quantized DPCM signal on the output side
and a second output that outputs a signal obtained by multiplying the quantized DPCM signal by a prediction coefficient; a first adder 5, a first delay element 7, and a first delay element 7;
a multiplier 12, and the first multiplier 12
The output of the first delay element 7 is multiplied by the prediction coefficient, and this output is input to the first adder 5 together with the first output of the quantizer 10. a predicted value detection loop that inputs an output to the first delay element 7 to detect a predicted value; a PCM signal is input to the first input, and a second output of the quantizer 10 is input to the second input; The signal delayed by the first delay element 7 and the signal multiplied by the prediction count by the second multiplier 11 are input to the third input, and each bit of each of the first, second, and third inputs is input to the third input. a 3-input 2-output digital-to-digital converter 1 that adds the addition result and a carry value for each time;
a second adder 2 to which the output of the two-input digital-to-digital converter 1 is applied and adds the two outputs; and a second delay element 3 to which the output of the second adder 2 is applied and delays the signal. and,