JPH0214140U - - Google Patents
Info
- Publication number
- JPH0214140U JPH0214140U JP1988093148U JP9314888U JPH0214140U JP H0214140 U JPH0214140 U JP H0214140U JP 1988093148 U JP1988093148 U JP 1988093148U JP 9314888 U JP9314888 U JP 9314888U JP H0214140 U JPH0214140 U JP H0214140U
- Authority
- JP
- Japan
- Prior art keywords
- state
- processing
- flip
- flop
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図は本発明の一実施例の処理状況表示機能
付きプロセツサの構成を示すブロツク図、第２図
は第１図のプロセツサの動作を説明するための波
形図である。
１……プロセツサ、２……割込み信号でセツト
される割込みフリツプ・フロツプ、３……入力ポ
ート、４……出力ポート、５……所定周期で発生
されプロセツサ１に所定の処理を要求する割込み
信号の入力端子、６……発光ダイオード、７……
処理状況表示信号の出力端子。
FIG. 1 is a block diagram showing the configuration of a processor with a processing status display function according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the processor shown in FIG. 1... Processor, 2... Interrupt flip-flop set by an interrupt signal, 3... Input port, 4... Output port, 5... Interrupt signal generated at a predetermined period and requesting processor 1 to perform a predetermined process. input terminal, 6... light emitting diode, 7...
Output terminal for processing status display signal.
Claims (1)
トされるフリツプ・フロツプと、 アイドル状態において前記フリツプ・フロツプ
のセツト状態を検出するとこれをリセツト状態に
変更したのち所定の処理を開始し、この所定の処
理の終了に際し前記フリツプ・フロツプの二値状
態を読取り処理状況を表示する信号として出力す
るプロセツサとで構成される処理状況表示機能付
きプロセツサ。[Scope of Claim for Utility Model Registration] A flip-flop that is set by a processing start command generated at a predetermined period, and when the set state of the flip-flop is detected in an idle state, it is changed to a reset state, and then a predetermined state is set. A processor with a processing status display function, comprising a processor that starts processing and, upon completion of the predetermined processing, reads the binary state of the flip-flop and outputs it as a signal indicating the processing status.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988093148U JPH0214140U (en) | 1988-07-13 | 1988-07-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988093148U JPH0214140U (en) | 1988-07-13 | 1988-07-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0214140U true JPH0214140U (en) | 1990-01-29 |
Family
ID=31317597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988093148U Pending JPH0214140U (en) | 1988-07-13 | 1988-07-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0214140U (en) |
-
1988
- 1988-07-13 JP JP1988093148U patent/JPH0214140U/ja active Pending
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