JPH02144939A - Transistor wiring connection structure - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring connection structure for a transistor in which a wiring formed on an insulating film covering the transistor is connected to an electrode of the transistor.

[Conventional technology]

Wiring formed on an insulating film covering a transistor is generally connected to an electrode of the transistor through a contact hole provided in the insulating film.

FIG. 7 shows the wiring connection structure of a conventional transistor, and here shows the connection structure of wiring connected to the source and drain electrodes of an inverted stagger type thin film transistor.

In FIG. 7, reference numeral 1 denotes an insulating substrate made of a glass plate or the like, and an inverted staggered thin film transistor T is formed on this insulating substrate 1. In FIG. This inverted staggered thin film transistor T has a gate electrode G formed on an insulating substrate 1.
and a gate insulating film 2 formed on this gate electrode G.
A 1-a-S1 semiconductor layer 3 is formed on this gate insulating film 2 to face the gate electrode G, and a source and a drain are formed on this semiconductor layer 3 with a channel part in between. The n''-a-31 layer 4 which becomes the area and this n''
It consists of a source electrode S and a drain electrode formed on the -a-5i layer 4. Note that the gate electrode G is connected to a gate wiring (not shown) formed on the substrate 1.

Further, an insulating film 5 covering the thin film transistor T is formed on the substrate 1 on which the thin film transistor T is formed, and the source electrode S and drain electrode of the thin film transistor T are connected to the wiring ( source wiring and drain wiring) 7. This wiring 7
is formed by depositing a wiring metal such as A11 on the insulating film 5 by a plating method or a sputtering method, and patterning this metal film. Electrode S
, D are also deposited and filled in the contact holes 6 formed corresponding to the contact holes 6, and the wiring 7 is connected to the source electrode S and the drain electrode of the thin film transistor T via the contact metal layer 7a filled in the contact hole 6. has been done.

Although Fig. 7 shows the wiring connection structure of an inverted staggered thin film transistor, it is possible to The formed wiring is also connected to the electrode of the transistor in the same manner as above.

[Problem to be solved by the invention]

However, in the conventional transistor wiring connection structure, the wiring 7 formed on the insulating film 5 covering the transistor T is connected to the transistor T via the contact metal layer 7a filled in the contact hole 6 of the insulating film 5. Electrode (7th
In the figure, the wiring is connected to the source and drain electrodes S and D), so in order to reliably connect the wiring 7 and the electrode of the transistor T, this wiring is It is necessary to deposit the metal sufficiently thicker than the depth of the contact hole 6. The deposited thickness of this wiring metal is generally required to be about twice the depth of the contact hole 6. The insulating film 5 is made as thick as possible in order to reduce the capacitance between the wiring 7 formed thereon and the gate wiring on the substrate 1, and to reliably prevent a short circuit between the wiring 7 and the gate wiring. However, if the insulating film 5 is made thicker in this manner, the depth of the contact hole 6 provided in the insulating film 5 also becomes larger, and the deposited thickness of the wiring metal also becomes thicker. Therefore, in the conventional wiring connection structure described above, it takes time to deposit the wiring metal on the insulating film 5, and the wiring metal film deposited on the insulating film 5 is patterned to form the wiring 7. At the same time, the thickness of this wiring metal film is large, making patterning troublesome and also making it difficult to miniaturize the wiring.

The present invention has been made in view of the above-mentioned circumstances, and its object is to connect wiring formed on an insulating film covering a transistor to a contact hole formed in the insulating film of the transistor. Although the wiring is connected to the electrode, the wiring can be reliably electrically connected to the electrode of the transistor without thickly depositing the metal that will become the wiring on the insulating film and the contact metal layer in the contact hole. A wiring connection for a transistor that can reduce the deposition thickness of the metal described above to shorten the deposition time, facilitate patterning of the deposited metal film that becomes the wiring, and also enable miniaturization of the wiring. It's about providing structure.

[Means to solve the problem]

In order to achieve the above object, the present invention forms an insulating film covering a transistor with an insulating material capable of metal diffusion, and forms contact holes in this insulating film corresponding to the electrodes of the transistor. A metal diffusion layer in which a conductive metal is diffused into the insulating film is formed in the contact hole forming portion of the film from the inner peripheral surface of the contact hole to the surface of the insulating film around the contact hole, and is formed on the insulating film. A wiring is formed, a part of which overlaps the metal diffusion layer around the contact hole, and a contact metal layer made of the same metal as the wiring is formed at the inner bottom of the contact hole, and is connected to the electrode of the transistor and the metal diffusion layer. It is formed in contact with the metal diffusion layer on the inner peripheral surface of the contact hole.

[Effect]

That is, in the wiring connection structure of the transistor of the present invention, a conductive metal is diffused into the contact hole forming portion of the insulating film to form a metal diffusion layer extending from the inner peripheral surface of the contact hole to the surface of the insulating film around the contact hole. At the same time,
A portion of the wiring formed on the insulating film is formed so as to overlap the metal diffusion layer around the contact hole, thereby electrically connecting the wiring and the metal diffusion layer, and further forming a conductive connection between the wiring and the metal diffusion layer. When depositing the metal that will become the wiring above, this metal is simultaneously deposited on the inner bottom of the contact hole to form a contact metal layer on the inner bottom of the contact hole. The metal diffusion layer on the inner peripheral surface of the hole and the electrode of the transistor are reliably electrically connected. Therefore, according to the present invention, although the wiring formed on the insulating film covering the transistor is connected to the electrode of the transistor through the contact hole formed in the insulating film,
Without thickly depositing the metal that will become the wiring on the insulating film and the contact metal layer in the contact hole, the wiring can be connected to the electrode of the transistor through the conductive metal diffused into the contact hole forming portion of the insulating film. A reliable continuity connection can be made. According to the present invention, it is possible to reduce the deposition thickness of the metal that becomes the contact metal layer in the wiring and the contact hole, so the time for depositing this metal can be shortened. Patterning of the deposited metal film that will become wiring can be easily performed, and the wiring can also be miniaturized.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

1 and 2 show a first embodiment of the present invention, and this embodiment is applied when the transistor is an inverted staggered thin film transistor.

In FIG. 1, 1 is an insulating substrate made of a glass plate or the like, and T is an inverted staggered thin film transistor formed on the insulating substrate 1. In FIG. Note that this inverted staggered thin film transistor T has the same structure as the thin film transistor T shown in FIG. 7, so its description will be omitted by giving the same reference numerals in the figure.

Reference numeral 8 denotes an insulating film that covers the thin film transistor T, and the transparent insulating film 8 is made of a transparent insulating material capable of diffusing metal, such as SOG (spin-on glass), and has a thickness of about 11. Insulating film 8 made of this SOG
A contact hole 9 having a depth reaching the source and drain electrodes S and D is formed in correspondence with the source and drain electrodes S and D of the thin film transistor T, respectively. Reference numeral 10 denotes a diffusion prevention film formed on the insulating film 8, and the diffusion prevention film 1o has a diameter larger than the upper end of the contact hole 9, corresponding to the contact hole forming portion of the insulation film 8. A slightly larger opening 11 is provided. This diffusion prevention film 14 is provided to regulate a metal diffusion region when metal is diffused into the insulating film 8 to form a metal diffusion layer 8a, which will be described later. It is made of an insulating material that is difficult to diffuse, such as SIN. Then, a conductive metal such as ITO is diffused into the insulating film 8 in a portion of the insulating film 8 that is not covered with the diffusion blocking film 10, that is, in a contact hole formation portion corresponding to the opening 11 of the diffusion blocking film 10. A metal diffusion layer 8a is formed extending from the inner peripheral surface of the contact hole 9 to the surface of the insulating film 8 around the contact hole. Reference numeral 12 denotes a wiring made of a conductive metal such as AM formed on the insulating film 8, and a part of the wiring 12 is formed overlapping the metal diffusion layer 8a around the contact hole 9. and is electrically connected to this metal diffusion layer 8a. Also, 12a
is a contact metal layer formed at the inner bottom of the contact hole 9. As shown in FIG. This contact metal layer 12a is made of the same metal as the wiring 12, and the contact metal layer 12a is made of the same metal as the wiring 12, and is
are formed in contact with the source and drain electrodes S and D and the metal diffusion layer 8a on the inner peripheral surface of the contact hole 9, and the source and drain electrodes S and D and the metal diffusion layer 8a on the inner peripheral surface of the contact hole are formed in contact with each other. and are electrically connected.

FIG. 2 shows the method of forming the metal diffusion layer 8a, the wiring 12, and the contact metal layer 12a in the order of steps, and these are formed as follows.

First, a thin film transistor T is formed on an insulating substrate 1 by a well-known method.
After forming SOG on this substrate 1, a transparent insulating film (SOG film) 8 is formed as shown in FIG. After forming contact holes 9 in this insulating film 8 by etching to correspond to the source and drain electrodes S and D of the thin film transistor T, SIN is formed on the insulating film 8 by plasma CVD.
Figure 2 (Fig. 2)
As shown in a), a diffusion blocking film 10 is formed, and an opening 11 is formed in the diffusion blocking film 10 by etching to expose the contact hole forming portion of the insulating film 8.

Next, IT is used as a conductive metal to be diffused into the insulating film 8.
By sputtering O, an ITO film a is deposited on the surface of the insulating film 8 and the inner surface of the contact hole 9 as shown by the chain line in FIG. 2(b). This ITO sputtering is performed at a substrate temperature of about 300°C. When this ITO sputtering is performed, the ITO film a is deposited on the surface of the insulating film 8 and the inner surface of the contact hole 9, and at the same time, the deposited ITO is deposited on the part of the insulating film 8 that is not covered with the diffusion prevention film 10. As shown in FIG.
) is formed as shown. In addition, I T 0I14
Although a is also deposited on the source and drain electrodes S and D exposed in the diffusion prevention film 10 and the contact hole 9,
Since the diffusion prevention film 10 is a SIN film in which metal is difficult to diffuse, ITO hardly diffuses into the diffusion prevention film 10, and the ITOa deposited on the source and drain electrodes S and D is absorbed by the electrode S. , D. This sputtering of ITO affects the diffusion depth of ITO into the insulating film 8, that is, the metal diffusion layer 8a to be formed.
This process is continued until the layer thickness becomes sufficient as a conductive film (approximately 500 layers). In this case, after the ITO is diffused into the insulating film 8 by the ITO sputtering, if the substrate 1 is heated again to about 300° C., the depth of ITO diffusion into the insulating film 8 can be further increased. Deepen it,
A sufficient layer thickness of the metal diffusion layer 8a can be ensured.

Next, I deposited on the diffusion prevention film 10 and the insulating film 8
TOIllia, Hcj2: HNO3: H20
-1: o, os: The entire surface was etched at 35° C. using an etching solution of 1 to remove the IT OM on the diffusion prevention film 10.
Remove a. If this entire surface is etched, SIN
The surface of the diffusion blocking film 10 is etched for about 2 minutes to recover its insulating properties, and the metal diffusion layers 8a in each contact hole portion of the insulating film 8 are separated from each other.

In this case, not only the ITO film a on the diffusion blocking film 10 but also the ITOIllia deposited on the insulating film 8 is etched, but the metal diffusion layer 8a of the insulating film 8 remains almost unetched. Even when the surface 10 recovers its insulating properties, the portion of the insulating film 8 where the metal diffusion layer is formed maintains conductivity with a resistance value of several Ω. Furthermore, when the entire surface is etched, the ITO film a deposited on the bottom surface of the contact hole 9, that is, on the source and drain electrodes S and D of the thin film transistor T, is also etched away.
The drain electrodes S and D remain without being etched.

The metal diffusion layer 8a thus formed has its lower end surface connected to the source and drain electrodes S of the thin film transistor T.
, D, and therefore this metal diffusion layer 8
a are the source and drain electrodes S and D of the thin film transistor T
This becomes a contact layer that connects the wiring 12 formed on the insulating film 8.

Next, a conductive metal (for example, l1l) is deposited by a plating method or a sputtering method to form a metal film that will become the wiring 12 on the diffusion prevention film 10 and the insulating film 8 as shown in FIG. 2(c).
At the same time, the contact hole 9 is formed as shown in FIG.
The metal is also deposited inside the contact hole 9 to form a contact metal layer 12a at the inner bottom of the contact hole 9. The deposited thickness of this metal should be selected to be about twice the thickness of the diffusion prevention film 10. If the thickness of the diffusion prevention film 10 is 1000, the thickness of the metal deposited is about 2000. If the metal is deposited on the surface of the diffusion prevention film 10 and the surface of the insulating film 8, the metal will be deposited to a sufficient thickness even on the stepped portion between the surface of the diffusion prevention film 10 and the surface of the insulating film 8, and will be continuous from the top of the diffusion prevention film 10 to the top of the insulation film 8. It is possible to form a metal film without any disconnections. Further, if the metal is deposited to this thickness, the contact metal layer 12a deposited in the contact hole 9 will be able to form the source of the thin film transistor T,
Drain electrode S.

D and the metal diffusion layer 8a on the inner circumferential surface of the contact hole 9 with a sufficient contact area, and the source,
Metal diffusion layer 8a in conductive contact with drain electrodes S and D
are connected to the source and drain electrodes S and D more reliably.

Thereafter, the metal film deposited on the diffusion prevention film 10 and the insulating film 8 is patterned to form wirings (source wiring and drain wiring) 12 as shown in FIG. This patterning of the metal film is performed until the thickness of the metal film is approximately 2,000 mm.
Since it is thin, it can be easily performed, and therefore, fine wiring 12 can also be formed.

That is, in the wiring connection structure, a conductive metal (ITO) is diffused into the contact hole forming portion of the insulating film 8 to form a metal diffusion layer 8a extending from the inner peripheral surface of the contact hole 9 to the surface of the insulating film around the contact hole. At the same time, the wiring 12 formed on the insulating film 8 is formed so that a part thereof overlaps the metal diffusion layer 8a around the contact hole 9, so that the wiring 12 and the metal diffusion layer 8a are separated. When the metal which becomes the wiring 12 is deposited on the insulating film 8, this metal is simultaneously deposited on the inner bottom of the contact hole 9, and the contact metal is formed on the inner bottom of the contact hole 9. By forming the layer 12a, the contact metal layer 12a connects the metal diffusion layer 8a on the inner peripheral surface of the contact hole and the source of the thin film transistor T.
The drain electrodes S and D are reliably electrically connected.

Therefore, according to this wiring connection structure, the wiring 12 formed on the insulating film 8 covering the thin film transistor T is connected to the source and drain electrodes S and D of the thin film transistor T through the contact hole 9 formed in the insulating film 8. However, the wiring 12 can be diffused and formed in the contact hole forming portion of the insulating film 8 without depositing a thick metal to form the wiring 12 on the insulating film 8 and the contact metal layer 12a in the contact hole 9. It is possible to ensure conductive connection to the source and drain electrodes S and D of the thin film transistor T via the conductive metal 8a. According to the wiring connection structure, the wiring 12 and the contact metal layer 12
Since it is possible to reduce the thickness of the metal deposited as a,
This can shorten the metal deposition time and also
Patterning of the deposited metal film that will become the wiring 12 can be easily performed, and the wiring 12 can also be miniaturized.

Although the above embodiment describes the connection structure of the wiring connected to the source and drain electrodes of an inverted staggered thin film transistor, the present invention can also be applied to thin film transistors with other structures and ordinary transistors using an Sl single crystal substrate. Of course, it can also be applied to wiring connection structures.

3 to 5 show second to fourth embodiments of the present invention, and FIG. 3 shows the connection structure of the wiring 12 connected to the gate electrode G and drain electrode of the staggered thin film transistor T. FIG. 4 shows the connection structure of the wiring 12 connected to the gate electrode G and drain electrode of the Kobranar thin film transistor T, and FIG. The connection structure of the wiring 12 is shown.

The basic configuration of each embodiment shown in FIGS. 3 to 5 is the same as that of the first embodiment described above, and therefore the explanation thereof will be omitted by assigning the same reference numerals to the figures. 3 and 5, reference numeral 13 denotes an electrode (drain electrode D1 in FIG. 3 and source electrode S and drain electrode D
) is a contact metal film formed on the n''-a-5i layer 4. This contact metal film 13 is deposited after forming the metal diffusion layer 8a on the insulating film 8, and therefore The contact metal film 13 is the diffusion prevention film 10
The contact metal film 13 is also formed on the insulating film 8, and in FIG. 3, the contact metal film 13 is also formed on the gate electrode G.

Further, FIG. 6 shows a fifth embodiment of the present invention,
This embodiment is an example in which the transistor uses an 81 single crystal substrate. In Figure 6,
14 is an S+ single crystal substrate, Tl is an n-MOS transistor, Tl is a p-MOS transistor, and G, S, and D are the gate, source, and drain electrodes of each transistor TI and T2. Further, the gate electrode G of each transistor Tl, T2 is a polySt electrode, and the source and drain electrodes S
, D are metal electrodes, and the nMOS transistor T
l source electrode sf1! :p-MOS transistor T2
The drain electrodes are connected to the picture electrodes S and D by an integral connection wiring 15. Further, a contact metal film 16 is formed on the gate electrode G of the p-MOS transistor T2, and the gate electrode G of the n-MOS transistor T1 is connected to the gate wiring 17 formed thereon. The drain electrode of this n-MOS) transistor Tl is connected to a drain wiring (not shown). Note that 2 is a gate insulating film. Also, the above transistor T
An insulating film 8 made of SOG is formed on 1 and Tl, and a diffusion prevention film 10 made of SIN is formed thereon. Wires 12 are formed on the diffusion prevention film 10 and the insulating film 8 to be connected to the gate electrode G and source electrode S of the p-MOS transistor Tl and the connection wire 15, respectively. 12 is connected to the gate electrode G, source electrode S, and connection wiring 15 in the same manner as in the first embodiment described above. In addition,
Since the configuration of the connecting portion of the wiring 12 is the same as that in the first embodiment, a description thereof will be omitted by assigning the same reference numerals to the drawings.

In each of the above embodiments, the insulating film 8 is an SOG film, but the insulating film 8 is not limited to SOG, and may be any material that allows metal to be diffused. The metal is not limited to ITO either. Also,
Diffusion prevention film 10 regulating the diffusion region of metal into the insulating film 8
However, the material is not limited to the SIN film as long as it is difficult for metal diffusion to occur. Further, in each of the above embodiments, the diffusion prevention film 10 on the insulating film 8 is left as is, but the diffusion prevention film 10 may be removed after the metal diffusion layer 8a is formed on the insulation film 8. If the diffusion prevention film 10 is removed in this way, the surface of the insulating film 8 becomes a flat surface without any steps, so that the thickness of the deposited metal that will become the wiring 12 can be further reduced.

〔Effect of the invention〕

In the wiring connection structure of a transistor of the present invention, an insulating film covering the transistor is formed of an insulating material capable of metal diffusion, contact holes are formed in this insulating film to correspond to electrodes of the transistor, and the insulating film A metal diffusion layer in which a conductive metal is diffused into the insulating film is formed in the contact hole forming portion from the inner circumferential surface of the contact hole to the surface of the insulating film around the contact hole, and a wiring is formed on the insulating film. , a part of which overlaps the metal diffusion layer around the contact hole, and a contact metal layer made of the same metal as the wiring at the inner bottom of the contact hole, which connects the electrode of the transistor and the contact. Since it is formed in contact with the metal diffusion layer on the inner peripheral surface of the hole, the wiring formed on the insulating film covering the transistor is connected to the electrode of the transistor at the contact hole formed in the insulating film. Although it is
The wiring can be reliably electrically connected to the electrode of the transistor without thickly depositing the metal that becomes the wiring on the insulating film and the contact metal layer in the contact hole. Therefore, the deposition thickness of the metal can be reduced. By making it thinner, the deposition time can be shortened, and the deposited metal film that will become the wiring can be easily patterned, and the wiring can also be miniaturized.

[Brief explanation of the drawing]

1 and 2 are a cross-sectional view of a transistor showing a first embodiment of the present invention and a process diagram for forming a metal diffusion layer and a wiring/contact metal layer, and FIGS. FIG. 7 is a cross-sectional view of a transistor showing a conventional wiring connection structure. T, Tl, T2...transistor, G...gate electrode, S...source electrode, D...drain electrode, 8
...Insulating film (SOG film) 8a...Metal diffusion layer,
9... Contact hole, 10... Diffusion prevention film (St
(N film), 12... Wiring, 12a... Contact metal layer.

Claims (1)

[Claims] In a structure in which a wiring formed on an insulating film covering a transistor is connected to an electrode of the transistor, the insulating film covering the transistor is formed of an insulating material capable of diffusing metal, and the insulating film is coated with the transistor. A contact hole is formed corresponding to the electrode, and a metal diffusion layer in which a conductive metal is diffused into the insulating film is applied to the contact hole forming portion of the insulating film from the inner circumferential surface of the contact hole to the insulation around the contact hole. A wiring is formed over the film surface and formed on the insulating film, with a part thereof overlapping the metal diffusion layer around the contact hole, and
A transistor characterized in that a contact metal layer made of the same metal as the wiring is formed at the inner bottom of the contact hole in contact with an electrode of the transistor and the metal diffusion layer on the inner peripheral surface of the contact hole. wiring connection structure.