JPH02145443U

JPH02145443U -

Info

Publication number: JPH02145443U
Application number: JP5353189U
Authority: JP
Priority date: 1989-05-10
Filing date: 1989-05-10
Publication date: 1990-12-10

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例であるパリテイチ
エツカジエネレータ素子に関する機能および構成
図で、同図ａは端子図で１はパリテイチエツカジ
エネレータ素子、２はその入力信号、３は出力制
御信号、４は入力データが偶数であることを示す
出力端子、５は入力データが奇数であることを示
す出力端子、同図ｂは真理値表、同図ｃは回路図
で６はパリテイチエツカ部、７と８は出力制御を
行なうアンド・ゲートである。第２図は従来のパ
リテイチエツカジエネレータ素子の構成および機
能図の一例で、同図ａは端子図で１はパリテイチ
エツカジエネレータ素子、２はその入力信号、４
は入力データが偶数であることを示す出力端子、
５は入力データが奇数であることを示す出力端子
、同図ｂはその真理値表であり、同図ｃはそのタ
イミング・チヤートである。 Fig. 1 is a functional and configuration diagram of a parity checker generator element that is an embodiment of this invention.A in the figure is a terminal diagram, 1 is the parity checker generator element, 2 is its input signal, and 3 is the output. Control signal, 4 is an output terminal that indicates that the input data is an even number, 5 is an output terminal that indicates that the input data is an odd number, b is the truth table, c is the circuit diagram, and 6 is the parity checker section. , 7 and 8 are AND gates for controlling output. Figure 2 is an example of the configuration and functional diagram of a conventional parity checker generator element, in which a is a terminal diagram, 1 is the parity checker generator element, 2 is its input signal, 4 is a terminal diagram.
is an output terminal indicating that the input data is even,
5 is an output terminal indicating that the input data is an odd number, b is its truth table, and c is its timing chart.

補正平１．８．１１図面の簡単な説明を次のように補正する。明細書の第６頁第８行の「同図（ｂ）は真理値
表」を「同図（ｂ）は真理値を示す図表」と補正
する。明細書の第６頁第１６行の「同図（ｂ）はその
真理値表」を「同図（ｂ）はその真理値を示す図
表」と補正する。Amendment 1.8.11. The brief description of the drawing is amended as follows. ``The figure (b) is a truth value table'' on page 6, line 8 of the specification is amended to read ``the figure (b) is a table showing truth values.'' In the 6th page, line 16 of the specification, ``Figure (b) is a truth table of the same'' is amended to ``Figure (b) is a chart showing the truth values of the same.''

Claims

[Scope of utility model registration request]

In the parity chain generator element,
comprising a data input terminal, a generation circuit for determining whether the number of significant data at the input terminal is an even number or an odd number, and a control input terminal capable of controlling the output of the generation circuit;
A parity check generator element comprising an output terminal from which a result of a generating circuit is output under control of the control input terminal.