JPH02146629U - - Google Patents
Info
- Publication number
- JPH02146629U JPH02146629U JP5540489U JP5540489U JPH02146629U JP H02146629 U JPH02146629 U JP H02146629U JP 5540489 U JP5540489 U JP 5540489U JP 5540489 U JP5540489 U JP 5540489U JP H02146629 U JPH02146629 U JP H02146629U
- Authority
- JP
- Japan
- Prior art keywords
- line
- gate
- drain
- liquid crystal
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Transforming Electric Information Into Light Information (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Description
第１図は本考案によるＴＦＴ液晶表示パネルの
構成図、第２図は従来のＴＦＴ液晶表示パネルの
構成図である。
Ｇ１，Ｇ２，…，…ゲートライン、ＤＡ１，Ｄ
Ａ２，…，…第１のドレインライン、ＤＢ１，Ｄ
Ｂ２，…，…第２のドレインライン、Ｔ１１，Ｔ
１２，…，Ｔ２１，Ｔ２２，…，…薄膜トランジ
スタ、Ｃ１１，Ｃ１２，…，Ｃ２１，Ｃ２２，…
，…液晶表示素子。
FIG. 1 is a block diagram of a TFT liquid crystal display panel according to the present invention, and FIG. 2 is a block diagram of a conventional TFT liquid crystal display panel. G1, G2,...,...gate line, DA1, D
A2,...,...first drain line, DB1,D
B2,...,...second drain line, T11,T
12, ..., T21, T22, ..., ... thin film transistor, C11, C12, ..., C21, C22, ...
,...Liquid crystal display element.
Claims (1)
れらのゲートラインの奇数番、偶数番にそれぞれ
対応してマトリクス状に配置される第１及び第２
のドレインラインと、上記ゲートラインと第１、
第２のドレインラインの各交点部分に設けられ、
対応するゲートライン及び第１、第２のドレイン
ラインにゲート電極及びドレイン電極がそれぞれ
接続されるスイツチイング用の薄膜トランジスタ
と、これらの薄膜トランジスタによりそれぞれ駆
動される液晶表示素子とを具備したことを特徴と
するとＴＦＴ液晶表示パネル。 (2) 平行配置される複数のゲートラインと、こ
れらのゲートラインの奇数番、偶数番にそれぞれ
対応してマトリクス状に配置される第１及び第２
のドレインラインと、上記ゲートラインと第１、
第２のドレインラインの各交点部分に配置され、
対応するゲートライン及び第１、第２のドレイン
ラインにゲート電極及びドレイン電極がそれぞれ
接続されるスイツチイング用の薄膜トランジスタ
と、これらの薄膜トランジスタによりそれぞれ駆
動され液晶表示素子と、上記第１のドレインライ
ンに映像信号を供給し、第２のドレインラインに
各ライン間を補間する補間映像信号を供給する映
像信号供給手段と、上記ゲートラインを２ライン
づつ順次走査する走査手段とを具備したことを特
徴とするＴＦＴ液晶表示パネル。[Claims for Utility Model Registration] (1) A plurality of gate lines arranged in parallel, and first and second gate lines arranged in a matrix corresponding to odd-numbered and even-numbered gate lines, respectively.
the drain line, the gate line and the first,
provided at each intersection of the second drain line,
The present invention is characterized by comprising a switching thin film transistor whose gate electrode and drain electrode are respectively connected to a corresponding gate line and first and second drain lines, and a liquid crystal display element which is driven by each of these thin film transistors. Then there is a TFT liquid crystal display panel. (2) A plurality of gate lines arranged in parallel, and first and second gate lines arranged in a matrix corresponding to odd-numbered and even-numbered gate lines, respectively.
the drain line, the gate line and the first,
located at each intersection of the second drain line,
A switching thin film transistor whose gate electrode and drain electrode are respectively connected to the corresponding gate line and the first and second drain lines, a liquid crystal display element driven by these thin film transistors, and a liquid crystal display element connected to the first drain line. It is characterized by comprising a video signal supply means for supplying a video signal and supplying an interpolated video signal for interpolating between each line to the second drain line, and a scanning means for sequentially scanning the gate line two lines at a time. TFT liquid crystal display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5540489U JPH02146629U (en) | 1989-05-15 | 1989-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5540489U JPH02146629U (en) | 1989-05-15 | 1989-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02146629U true JPH02146629U (en) | 1990-12-12 |
Family
ID=31578324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5540489U Pending JPH02146629U (en) | 1989-05-15 | 1989-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02146629U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011033889A (en) * | 2009-08-03 | 2011-02-17 | Hitachi Displays Ltd | Liquid crystal display device |
| WO2016079826A1 (en) * | 2014-11-19 | 2016-05-26 | 堺ディスプレイプロダクト株式会社 | Liquid crystal display device |
-
1989
- 1989-05-15 JP JP5540489U patent/JPH02146629U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011033889A (en) * | 2009-08-03 | 2011-02-17 | Hitachi Displays Ltd | Liquid crystal display device |
| WO2016079826A1 (en) * | 2014-11-19 | 2016-05-26 | 堺ディスプレイプロダクト株式会社 | Liquid crystal display device |
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