JPH021470B2 - - Google Patents

Description

Detailed Description of the Invention (A) Technical Field of the Invention The present invention relates to an image input device, and in particular to a white level follower used in a binarization circuit that converts a video signal obtained by scanning an image into a binary signal. Regarding circuits.

(B) Prior art and problems Figure 1 is an explanatory diagram illustrating how the white level follower circuit is used. 1 is a document, 2 is a character written on the document 1, 3 is a scanning line, and 4 is a white level follower circuit. It represents a virtual monitoring line, ie, a sub-scanning line, on which the level follower circuit monitors the white level corresponding to the coordinate x.

The document 1 is scanned according to the scanning line 3, and based on the video signal obtained by the scanning line, the characters 2
etc. will be extracted.

At this time, in determining the gradation of the dot on the sub-scanning line 4 having the coordinate x, the white level corresponding to the white background on the sub-scanning line 4 is determined, and the gradation is determined based on the white level. A decision is made.

FIG. 2 shows the configuration of a conventional example of a white level follower circuit, which is disclosed in Japanese Patent Application Laid-Open No. 57-210774 filed by the present applicant, and is used, for example, in image input devices. , the summary is as follows.

In FIG. 2, reference numeral 5 indicates a white level memory for sequentially determining the white level values included in the input video signal, and 6 indicates the content of the white level memory 5 corresponding to the white level in the input video signal that is currently input. White level tracking logic that changes to follow the white level, 7
8-1 is a D/A converter, and 8-1 is an output signal when the input video signal V is read from the white level memory 5 and the white level value W obtained via the D/A converter 7 is V≧W. The first comparison circuit that generates 8-2
8-3 is a second comparator circuit that generates an output signal when the input video signal V is V≧(1-m%)W with respect to the white level value W; 8-3 is a second comparator circuit that generates an output signal when the input video signal V is the white level value W; For W, V≧(1+n%)W
A third comparator circuit 9 that generates an output signal when A scanning number counter that generates an output signal for each count; 10 is a first comparison circuit 8;
-1, the output signal of the second comparator circuit 8-2, and the output signal of the third comparator circuit 8-3, the white level tracking logic 6 receives the output signal of the white level memory 5. A first instruction mode instructs to increase the content of the white level memory 5 by α%, a second instruction mode instructs to increase the content of the white level memory 5 by β% smaller than α, and a second instruction mode instructs to increase the content of the white level memory 5 by γ%. A third instruction mode that instructs to decrease the white level memory 5 and a fourth instruction mode that instructs not to change the contents of the white level memory 5 are generated, and the fourth instruction mode is generated, and the number of scans is It is an up-down logic that switches the fourth instruction mode to the third instruction mode when the counter 9 generates an output signal.

When the input video signal V corresponding to the dot on the sub-scanning line 4 shown in FIG. A specific white level value is read out, and after tracking, the white level that is the tracking result is read out, and the read white level value is supplied to the white level tracking logic 6 and the D/A.
It is supplied as an analog value via the converter 7 to a first comparison circuit 8-1, a second comparison circuit 8-2, and a third comparison circuit 8-3.

If the voltage level at the voltage dividing point a between resistors R1 and R2 is selected to be (1-m%) W, and the voltage level at the voltage dividing point b between resistors R3 and R4 is selected to be (1+n%) W, the input video signal V When the signal level of (a) V≧(1+n%)W, all of the first comparator circuit 8-1, the second comparator circuit 8-2, and the third comparator circuit 8-3 are (b) When (1+n%)W>V≧W, the first comparison circuit 8-1 and the second comparison circuit 8-2 generate output signals; (c) W >V≧(1-m%)W, only the second comparison circuit 8-2 generates an output signal; (d) When V<(1-m%)W, the first comparison circuit 8-2 generates an output signal. -1, the second comparator circuit 8-2, and the third comparator circuit 8-3 do not generate an output signal.

The up-down logic 10 operates as follows: (i) When the above condition (a) is met, the white level tracking logic 6
(ii) When the condition (b) is met, the white level tracking logic 6 outputs a first instruction mode signal "00" that instructs the content of the white level memory 5 to increase by α%. outputs a second instruction mode signal "01" instructing to increase the contents of the level memory 5 by β%; (iii) when the above condition (c) is met, the white level tracking logic 6
, a third instruction mode signal "10" instructs to reduce the contents of the white level memory 5 by γ%.
(iv) When the above condition (d) is met, the white level tracking logic 6
, a fourth instruction mode signal "11" is output for instructing not to change the contents of the white level memory 5, that is, to clamp it.

(v) Furthermore, when the scan number counter 9 generates this output signal based on the output signal generated for one scan period every 16 counts, the up-down logic 10 satisfies the condition (d). When this occurs, the fourth instruction mode signal "11" is switched to the third instruction mode signal "10" and output.

That is, the fourth instruction mode (iv) in the above conventional example is used when a black dot for a figure like A (for example, a character) shown in FIG. 3 occurs in the input video signal V in the image input device. Also, by not making the white level value W output from the white level memory 5 follow the black dot A, the gradation of the black dot can be determined correctly.

In addition, the function (v) above is provided in the image input device,
For example, when a white background on a document gradually turns gray due to a change in reflectance due to the flapping of the paper surface during paper feeding when inputting an image, characters such as B shown in Figure 4 may be added to this area. If there is a part, there will be a difference of more than a predetermined value (for example, m%) between the white level of the beginning (left side) part of the character and the white level of the end (right side) part of the character, and the end of the character (on the right), there is a risk that the area around the area becomes gray, so avoid the white level being clamped as shown in W' (indicated by the dashed line), and It is designed to change in stages.

However, according to such a conventional example, for a thin long line parallel to the sub-scanning direction, the white level value W gradually decreases with respect to the input video signal V, as shown in FIG. , will eventually reach the same level as the video signal V, and a problem arises in that such a straight line cannot be read from the middle.

Although such problems rarely occur in optical character reading devices (OCR), they often occur in image input devices.

(C) Object of the Invention The object of the present invention is to solve the problem in the conventional example, that is, to prevent line breakage when reading a thin long line parallel to the sub-scanning direction in the above-mentioned white level follower circuit.

(D) Structure of the Invention The white level follower circuit according to the present invention includes a white level memory for sequentially determining white level values included in an input video signal, and a white level memory for reading out the currently inputted input video signal from the white level memory. a first comparator circuit that generates an output signal when the input video signal that is currently inputted is equal to or higher than the white level value read out from the white level memory;
a second comparator circuit that generates an output signal when the white level value read from the white level memory is n% or more higher than the white level value read from the white level memory; a third comparison circuit, a signal generator that generates an output signal every predetermined number of scans, an output signal of the first comparison circuit, an output signal of the second comparison circuit, and the third comparison circuit; Instructs the white level tracking logic, which causes the content of the white level memory to follow the white level in the currently input video signal, to increase the content of the white level memory by α% in accordance with the output signal of the circuit. a first instruction mode that instructs to increase the content of the white level memory by β% smaller than the α%, and a third instruction mode that instructs to decrease the content of the white level memory by γ%. and a fourth instruction mode instructing not to change the contents of the white level memory, and when the fourth instruction mode is generated, the signal generator generates an output signal. In a white level follower circuit having an up-down logic for switching a fourth instruction mode to a third instruction mode when
a counting circuit that counts the output of the scan number counter up to a predetermined number of times when the outputs of the first to third comparison circuits are in the fourth instruction mode; A circuit for instructing to interrupt the switching to the third instruction mode is provided, and the white level memory is controlled in accordance with the instruction to interrupt the switching from the fourth instruction mode to the third instruction mode in the up-down logic. The contents are changed sequentially.

(E) Examples of the invention Hereinafter, the gist of the present invention will be specifically explained using examples.

FIG. 6 shows the configuration of an embodiment of the present invention, and the same reference numerals as in FIG. 2 showing the configuration of the conventional example refer to the same objects, and 11 indicates the output signal of the second comparison circuit 8-2. An AND circuit 12 calculates the logical product of the signal inverted by the NOT circuit 15 and the output signal of the scanning number counter 9; When the count value for each scanning line 4 reaches a predetermined value k, a counting circuit generates a control signal to the switching interrupt circuit 14 described later, and 13 is a shifter that stores the count value of the counting circuit 12 for each sub-scanning line 4. memory, 14 is the function of (v) above;
That is, switching from the fourth instruction mode signal "11" to the third instruction mode signal "10" is interrupted by the control signal generated by the counting circuit 12, and the switching is limited to k times. This is an interruption circuit.

With the above configuration, switching from the fourth instruction mode to the third instruction mode by the function (v) explained in the conventional example can be performed until the count value in the counting circuit 12 reaches k times in a row. Therefore, even if an input video signal V such as C shown in FIG. The switching is terminated at the k consecutive times.

Therefore, by selecting an appropriate value of k through experiments or the like, it is possible to prevent the white level value W from reaching the black level part C of the input video signal V, and to prevent the white level value W from reaching the black level part C of the input video signal V, and to prevent the white level value W from reaching the black level part C of the input video signal V, and to prevent You will be able to read lines correctly all the way to the end.

(F) Effects of the Invention As explained above, according to the present invention, line breakage when reading continuous thin long lines in the sub-scanning direction in the conventional example can be prevented, and it can also be applied to image input devices. This has the effect of providing a white level follower circuit.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of how a white level follower circuit is used, Figure 2 is a configuration diagram of a conventional example of a white level follower circuit, Figures 3 and 4 are explanatory diagrams of a conventional example of a white level follower circuit, and Figure 5 is a white level follower circuit. FIG. 6 is an explanatory diagram of problems in a conventional level follower circuit, FIG. 6 is a configuration diagram of an embodiment of the present invention, and FIG. 7 is an explanatory diagram of an embodiment of the present invention. In the drawing, 3 is a scanning line, 4 is a sub-scanning line, and 5 is a scanning line.
is white level memory, 6 is white level tracking logic,
8-1 is a first comparison circuit, 8-2 is a second comparison circuit, 8-3 is a third comparison circuit, 9 is a scanning number counter, 10 is an up-down logic, and 11 is an AND
circuit, 12 is a counting circuit, 14 is a switching interrupt circuit,
Reference numeral 15 indicates a negative circuit.

Claims (1)

[Claims] 1. A white level memory for sequentially determining the white level value included in the input video signal, and generating an output signal when the currently inputted input video signal is equal to or higher than the white level value read from the white level memory. a first comparator circuit; a second comparator circuit that generates an output signal when the currently input input video signal is less than m% of the white level value read from the white level memory; a third comparator circuit that generates an output signal when the video signal obtained is greater than or equal to an n% increase in the white level value read from the white level memory; and a signal generator that generates an output signal every predetermined number of scans. and the contents of the white level memory are determined according to the output signal of the first comparison circuit, the output signal of the second comparison circuit, and the output signal of the third comparison circuit. A first instruction mode instructs the white level tracking logic to follow the white level in the signal to increase the content of the white level memory by α%, and to increase the content of the white level memory by β smaller than the α%. %, a third instruction mode instructs to decrease the contents of the white level memory by γ%, and a fourth instruction mode instructs not to change the contents of the white level memory. an up-down logic that generates an instruction mode and, if the fourth instruction mode is generated, switches the fourth instruction mode to the third instruction mode when the signal generator generates an output signal; a counting circuit that counts the output of the scan number counter up to a predetermined number of times when the outputs of the first to third comparison circuits are in the fourth instruction mode;
A circuit for instructing interruption of switching from the fourth instruction mode to the third instruction mode in the up-down logic is provided to interrupt switching from the fourth instruction mode to the third instruction mode in the up-down logic. 1. A white level follower circuit that sequentially changes the contents of said white level memory in accordance with instructions from said white level follower circuit.