JPH02148221A - Microcontroller - Google Patents

Abstract

PURPOSE:To constitute the microcontroller so that a preceding instruction can be executed without decoding it again after the succeeding instruction is executed prior to the execution of the preceding instruction by saving information required for executing the instruction of a microprogram to the microprogram. CONSTITUTION:When it is designated to execute the succeeding instruction first, the present microaddress and information required for executing other instruction are saved to microstacks 6, 10 as they are, a micro-instruction output part 3 generates the outputs a specific micro-instruction, and the execution of the succeeding instruction is started. Subsequently, by instructing read-out of the microstacks 6, 10 in the micro-instruction outputted in the end of a microprogram of the succeeding instruction required for being executed first, the start address of the microprogram of the preceding saved instruction and information required for executing the instruction are read out of the microstacks 6, 10 and the preceding instruction is executed. In such a manner, after the succeeding instruction is executed, the preceding instruction can be executed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microcontroller for a microprogram-controlled computer.

BACKGROUND OF THE INVENTION Conventional microcontrollers include, for example, Introduction to Ultra LSI Systems (Baifukan 1981) pp.

227-231.

FIG. 2 shows a configuration diagram of this conventional microcontroller, in which 1 is an instruction register that holds machine language instructions;
is an instruction decoder that decodes the machine language instruction held in instruction register 1 and determines the start address of the microprogram; 3 is a control memory that stores the microprogram; and 4 holds an address for reading the microinstruction from control memory 3. 5 is an incrementer that adds +1 to the microaddress held in the second register 4, 6 is the first microstack that saves the microaddress output from incrementer 5, and 7 is a microaddress selector. An address selection section 8 controls the flow of the microprogram by determining the next microaddress by modifying the microbranch displacement specified by the microinstruction, and 8 is a second address selection section that holds additional information necessary for executing the microinstruction. 9 is an additional information modification unit that changes or modifies the additional information output from the second register 8 for execution of the next microinstruction; 10 is a second micro stack that saves the additional information output from the additional information modification unit 9; , 11 is an additional information selection unit that selects additional information to be held in the second register 8 in accordance with the flow of the microprogram. Here, additional information refers to various information necessary for microinstruction execution, such as register numbers, data sizes, and breakpoint information specified in machine language instructions, and is executed by embedding it in a part of the microinstruction. control the execution of instructions.

The operation of the conventional microcontroller configured as described above will be explained by taking as an example the case where machine language instructions A11B110 are sequentially applied.

First, the case where machine language instruction A is executed by sequentially issuing microinstructions Al-A2 and A3, and machine language instruction B is executed by sequentially issuing microinstructions B1-82 will be explained using FIG. . In Figure 3, the first
・A1 written in the second register is machine language instruction A
It represents the state of the first microinstruction (microaddress and corresponding additional information) of the microprogram for executing the microinstruction.

When machine language instruction A is input to instruction register 1 at clock 1, instruction decoder 2 decodes it and outputs microinstruction A1.
Outputs the micro address and additional information. If the microprogram that executes the machine language instruction before A ends at clock 1, then the microprogram A1 executes at clock 2.
The micro address and additional information are stored in the first register 4 and the second register.
The microinstruction A1 is input to the register 8, read out from the control memory 3, combined with additional information, and sent to the execution unit. Accordingly, machine language instruction B is stored in instruction register 1.
is input.

Since this microinstruction A1 is not the final instruction of the microprogram that executes the machine language instruction A, the address selection unit 7 selects the microaddress output from the incrementer 5, and the microaddress added by +1 by the incrementer 5 (microinstruction A2 micro address) is clock 3
is input to the first register 4. Similarly, the additional information selection unit 11 selects the additional information modified by the additional information modification unit 9 (additional information corresponding to microinstruction A2), and
is input into the second register 8. Microinstructions A1 and A2φA3 stored in the control memory 3 in this way
are sequentially output up to the final instruction A3. and clock 4
When the microinstruction read from the control memory 3 becomes the final instruction A3, the address selection section 7/additional information selection section 11 selects the decoding result of the machine language instruction B output from the instruction decoder 2, and selects the result of decoding the machine language instruction B output from the instruction decoder 2. Then, the state of microinstruction B1 is input to the second register 8, and processing of the new instruction is started.

Next, the case where the microinstruction A1 calls the microinstruction All.A12 by the microsubroutine call instruction will be described with reference to FIG.

When machine language instruction A is input to instruction register 1 at clock 1, microinstruction A1 is input at clock 2 as in the previous example.
is output. Since this micro-instruction A1 specifies micro-stack saving, the micro-address A2 (micro-address of micro-instruction A2) output from the incrementer 5 is saved in the first micro-stack 6, and the additional information is transferred to the second micro-stack 10. Additional information A2 (additional information corresponding to microinstruction A2) output by the modifier 9 is saved. Then, the address selection unit 7 selects the start address of the micro subroutine (micro address of micro instruction A11) (created by adding the displacement described in a part of micro instruction A1 to micro address A2, for example), and clocks 3, it is input to the first register 4 and the micro subroutine is executed.

When microinstruction A12 is output at clock 4, this microinstruction A12 specifies microstack return, so the microaddress of microinstruction A2 is read out from the first microstack 6, and the microinstruction is read out from the second microstack 10. Additional information corresponding to A2 is read. At this time, address selection section 7/additional information selection section 1
1 selects the output of the first microstack and the second microstack, and at clock 5, the state of microinstruction A2 is input to the first register 4 and second register 8, and processing starts from the next microinstruction after the microsubroutine call instruction. It will be restarted. The rest is the same as the previous explanation.

Problem to be Solved by the Invention However, in the above configuration, when the microinstruction of the micro subroutine call is executed, the current microaddress is incremented and saved in the microstack, and the additional information is also changed before being stored in the microstack. Therefore, it is not possible to save the start address and additional information to the microstack without outputting the microprogram that executes the machine language instruction, and then execute it from the start address of the original microprogram after executing other microinstructions. Can not. In other words, the information saved to the microstack is always information about the next state of the executed microinstruction, so it is necessary to save information about the initial state of the microprogram and then return it to the original state after executing the subsequent instruction. There was a problem in that execution could not be resumed from the saved state.

The process of not executing the decoded machine language instruction immediately, but after executing the subsequent machine language instruction, is
For example, it is effective in the multi-stage indirect mode adopted in TRONCHIP. Multi-stage indirect mode is a type of addressing mode used in machine language instructions, in which data is read from memory using the displacement value index register specified by the subsequent instruction, and the read data is specified as an address by the preceding instruction. Execute the operation to be performed. In other words, the subsequent instruction is an extension of the data addressing of the preceding instruction specifying the operation. Multiple subsequent instructions can be followed, and in that case, the memory load is repeated using the data read from memory as the base value and the value added to the displacement value and index register specified by the subsequent instruction as the address, resulting in a complicated process. This addressing mode is effective for accessing structural variables.

In view of this, the present invention provides a micro 1lilJ control device that executes the preceding instruction after executing the subsequent instruction when it is determined that the subsequent instruction needs to be executed first as a result of decoding the preceding machine language instruction. The purpose is to provide

Means for Solving the Problems The present invention provides a method for inputting an evacuation signal that instructs evacuation in the case of an instruction that cannot be executed until after the execution of a subsequent instruction, and does not instruct evacuation in other cases. a micro-instruction output unit that outputs a specific micro-instruction when the instruction is given, and otherwise outputs the micro-instruction stored in the micro-instruction read address; a first register that holds the micro-instruction read address; an incrementer that inputs the microaddress output from the first register, adds +1 and outputs the result; and an incrementer that inputs the microaddress outputted from the first register and the microaddress outputted from the incrementer, and the evacuation signal outputs the evacuation signal. A first selector that outputs the microaddress outputted from the first register when the instruction is given, and a microaddress outputted from the incrementer otherwise, and a first selector that outputs the microaddress outputted from the first selector; If the save signal instructs save or if the microinstruction output by the microinstruction output section is a save instruction, write the microaddress output by the first selector to the stack and save it; if the microinstruction is a return instruction, A first micro stack that reads and outputs the last saved micro address from the stack, a start address of a micro program that executes a machine language instruction, a micro address output by the incrementer 111j, and a micro address output by the first micro stack. an address selection section that receives addresses and microaddress modification information that modifies parts of these addresses and outputs the next microaddress held by the first register; an additional information modification unit that inputs the additional information output from the second register, modifies it in a form necessary for the execution of the next microinstruction, and outputs it; and the second register. The additional information output by the second register and the additional information output by the additional information modification unit are input, and if the save signal instructs saving, the additional information output by the second register is output, and otherwise, the additional information is modified. a second selector that outputs additional information outputted by the microinstruction unit; and a second selector that receives the additional information outputted from the second selector, and receives the additional information outputted by the second selector, and the save signal instructs saving or the microinstruction outputted by the microinstruction output unit is a save instruction. If the microinstruction is a return instruction, the additional information output from the second selector is written to the stack and saved, and if the microinstruction is a return instruction, the second microstack and machine language instruction are read out and outputted from the stack. Addition that takes as input the initial value of the additional information obtained by decoding, the additional information outputted by the additional information modification section, and the additional information outputted by the second micro stack, and outputs the additional information held next by the second register. This is a microcontroller equipped with an information selection section.

According to the above-described configuration, when the following instruction is specified to be executed first, the present invention saves the current microaddress and other information necessary for executing the instruction as is to the microstack, and stores the current microaddress. Generates and outputs a specific microinstruction in place of the microinstruction stored in the microinstruction. If the generated microinstruction is in the same format as the final instruction of the microprogram, by executing this microinstruction, the execution of the microprogram will be recognized as having ended, and the execution of subsequent instructions will begin. Then, by instructing the reading of the microstack in the microinstruction output at the end of the microprogram of the subsequent instruction that needs to be executed first, the start address of the microprogram of the preceding instruction saved in the microstack and the instruction Information necessary for execution is read from the microstack and the preceding instruction is executed.

Embodiment FIG. 1 shows a configuration diagram of a microcontroller in a first embodiment of the present invention. In FIG. 1, 1 is an instruction register that holds machine language instructions, and 2 is an instruction register 1.
an instruction decoder that decodes machine language instructions stored in
3 is a microinstruction output unit that outputs a microinstruction, 4 is a second register that holds a microaddress, 5 is an incrementer that adds +1 to the microaddress held in the second register 4, and 6 is a saver of the microaddress. a first micro stack; 7 is an address selection section that selects a micro address, modifies it with micro branch displacement specified by a micro instruction, determines the next micro address, and controls the flow of the micro program; 8;
is the second one that holds additional information necessary to execute the microinstruction
9 is an additional information modification unit that changes or modifies the additional information output from the second register 8 for execution of the next microinstruction; 10 is a second micro stack that saves the additional information; 11 is an additional information modifying unit for the flow of the microprogram; 2nd in total
Additional information selection unit 12 selects additional information to be held in register 8, and 12 holds an evacuation signal that instructs evacuation in the case of an instruction that cannot be executed until after executing a subsequent instruction, and does not instruct evacuation in other cases. 3rd register, 13 is a first selector that selects the microaddress to be saved to the first microstack 6, 14 is the second microstack 1
This is a second selector for selecting additional information to be saved to 0.

The operation of the microcontroller of this embodiment configured as described above will be described below, taking as an example the case where machine language instructions A, B, and C are sequentially given.

Machine language instruction A is a normal machine language instruction (instruction that does not require the subsequent machine language instruction to be executed first) and A111A2/A3
are issued in order, and machine language instruction B becomes B1.
- When executed by sequentially issuing microinstructions 82, it is exactly the same as the conventional microcontroller shown in FIG.

When the instruction decoder 2 decodes the machine language instruction A at clock 1, it does not instruct the save signal to save, and the save signal is input to the third register 12 at clock 2. The third register 12 inputs the save signal simultaneously when the first register 4 and the second register 8 input the output of the instruction decoder 2.

Next, even when microinstruction A1 calls microinstruction All・A12 with a microsubroutine call instruction, the operation of each register and microstack is
Same as the conventional microcontroller shown in the figure, when the micro subroutine call instruction A1 is output at clock 2, the first selector 13 selects the output of the incrementer 5, and the second selector 14 selects the output of the additional information modification unit 9. By selecting the output of , the state of the microinstruction A2 following the call instruction At is saved in each microstack.

Next, if machine language instruction A needs to execute the following machine language instruction B first (for example, if instruction B is an extension of the addressing of instruction A, then the jW f operation of instruction A is
A case in which data is read out from the memory using the data obtained by executing the above as an address will be described with reference to FIG.

When machine language instruction A is input to instruction register 1 at clock 1, instruction decoder 2 decodes it and outputs microinstruction A1.
The micro address and additional information of the micro address and additional information are output, and the save signal is instructed to save. Assuming that the microprogram that executes the machine language instruction before A ends at clock 1, the microaddress and additional information of microinstruction A1 are input to the first register 4 and second register 8 at clock 2, and the save signal is input to the second register 8. 3 register 12.

This time, since the save signal input to the third register 12 instructs saving, the first selector 13 directly selects the micro address output by the first register 4 instead of the micro address output by the incrementer 5. The second selector 14 directly selects the additional information output from the second register 8 instead of the additional information output from the additional information modification unit 9, and the second selector 14 directly selects the additional information output from the second register 8
evacuate to. In this way, the state of the microinstruction A1 instead of the microinstruction A2 can be saved by instructing the saving with the save signal this time.

At this time, since the save signal instructs saving, the microinstruction output section does not output the microinstruction A1 stored in the microaddress specified by the first register 4, but generates a specific microinstruction AO. Output. This microinstruction AO is the final instruction of the microprogram, such as A3 or B.
2 (for example, the bit indicating that it is the final microinstruction is 1), the address selection section 7 and additional information selection section 11 select the output of the instruction decoder 2. Then, the start address φ additional information/save signal of the first microinstruction B1 of the microprogram of machine language instruction B is input to each register, and execution of the microprogram of instruction B is started.

If machine language instruction B is the last of the subsequent instructions to be executed before machine language instruction A, then the last microinstruction B2 in the microprogram of instruction B is not in the form of the final instruction, but in the form of the first instruction.
This is an instruction to read saved information from the micro stack 6 and the second micro stack 10. When this microinstruction B2 is executed at clock 4, the state of microinstruction A1 saved in the first microstack 611 and second microstack 10 is read out, and the state of the microinstruction A1 saved in the first microstack 611 and second microstack 10 is read out, and the state of the microinstruction A1 is read out from the address selection unit 7.
The additional information selection unit 11 selects the output of each microstack, and the microaddress group additional information of the microinstruction A1 read from the microstack is input into the second register 8. execution begins.

As described above, according to this embodiment, by providing a function to select the start address of a microprogram and other information necessary for instruction execution and save it to the micro stack, the information can be saved in the micro stack prior to execution of the preceding machine language instruction. After the subsequent instruction is executed, the preceding instruction can be executed without having to decode it again.

In the first embodiment, the additional information is output from the instruction decoder, but the additional information is output from the machine language instruction input to the instruction register and the information obtained from the machine language instruction read capital without passing through the instruction decoder. You can also use it as Further, in this embodiment, the instruction decoder outputs only the microaddress and additional information, but a part of the microinstruction (for example, an instruction for controlling address calculation of an operand, etc.) may be outputted from the instruction decoder. However, the microinstructions that can be output from the instruction decoder are limited to instructions that do not need to be executed after the subsequent instruction is executed.

FIG. 6 shows a configuration diagram of a microcontroller in a second embodiment of the present invention. In FIG. 6, 5 indicates 11 which outputs the output of the first register 4 as is when the save signal instructs saving, and otherwise adds +1 and outputs the output.
This is a 0 adder, and the configuration and operation other than this are the same as the elements with the same numbers in the first embodiment shown in FIG.

In the microcontroller of this embodiment configured as described above, when the save signal held in the third register 12 instructs saving, the adder 110 converts the micro address output from the first register 4 as is ( +0) and the first micro stack 6 saves the micro address to the stack, thereby realizing the same function as the first embodiment.

As a third embodiment, the microinstruction output section 3 of FIG. 1 is constructed from the elements shown in FIG. 7.

In FIG. 7, 31 is a control memory that stores a microprogram, and 32 is a microinstruction generator that outputs the microinstructions output from the control memory 31 as is or generates and outputs specific microinstructions. The configuration and operation are the same as the first embodiment shown in FIG.

In the microcontroller of this embodiment configured as described above, when the save signal held in the third register 12 instructs saving, the control memory 31 stores the data in the micro address output from the first register 4. The functions of the microinstruction output unit 3 are realized by generating and outputting specific microinstructions in the microinstruction generation unit 32.

As a fourth embodiment, the microinstruction output section 3 of FIG. 1 is constructed from the elements shown in FIG. 8.

In FIG. 8, 31 is a microaddress generator that outputs the microaddress outputted by Runster 4 as it is, or generates and outputs a specific microaddress, and 32 is a control memory that stores a microprogram. (14) The structure and operation are the same as in the first embodiment shown in FIG.

In the microcontroller of this embodiment configured as described above, when the save signal held in the third register 12 instructs saving, the micro-address generation unit 31 generates a specific micro-address to control the control message. Output to Sosu 32. A specific microinstruction can be output by storing in advance a microinstruction to be output (in the third embodiment, a specific microinstruction generated by the microinstruction generation section) at that address in the control memory 32.

Normally, the read address of the control memory 32 has fewer bits than the microinstruction output from the control memory 32, so in this embodiment, the number of hardware required to generate a specific bit pattern can be reduced.

As a fifth embodiment, the 110 addition section 5 of FIG. 6 is constructed from the elements shown in FIG. 9. In Figure 9, 51
52 is an incrementer that increments the microaddress output from the first register 4 by +1, and 52 increments the least significant bit of the microaddress output from the incrementer 51.
This is a mask generation unit that masks and outputs the data. In this embodiment, the configuration other than the 110 adding section 5 is the second section shown in FIG.
This is the same as the embodiment.

In the microcontroller of this embodiment configured as described above, when the save signal held in the third register 12 does not instruct saving, the mask generation unit 52 converts the micro address output from the incrementer 51 into Output as is without masking. When the save signal held in the third register 12 instructs saving, the mask generation unit 52 masks the microaddress output from the incrementer 51 and sets the least significant bit to O. If you limit the start address of the microprogram to an even address in advance, the first
The least significant bit of the microprogram start address input to register 4 is always 0, and incrementer 5
The least significant bit of the microaddress outputted by 1 is 1. At that time, if the save signal instructs saving, the least significant bit of the microaddress output from the mask generation section S2 returns to 0, so that the +0 function of the 110 addition section 5 can be realized.

As described above, according to this embodiment, 110 additions, B((5
Since the function of the adder used for this can be limited to only +1, the amount of hardware can be reduced and high speed implementation can be achieved.

Note that in the fifth embodiment, the microaddress input to the address selection unit 7 is also taken from the output of the mask generation unit 52 as well as the input to the first microstack, but this is done by directly inputting the output of the incrementer 51. You may.

As described in detail, according to the present invention, the execution of a decoded machine language instruction is temporarily canceled and the subsequent machine language instruction is executed, without adding any special hardware, and the subsequent machine language instruction is executed. It is possible to easily start executing a canceled instruction after the execution is completed.

When using the multi-stage indirect mode, which is effective for accessing complex structure variables, the final memory address is determined by repeatedly executing memory reads specified by multiple subsequent instructions, and then specified by the preceding instruction. The process of executing the calculations performed can be realized using the microstack mechanism used in a normal microprogram control system, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcontroller according to a first embodiment of the present invention, FIG. 2 is a block diagram of a conventional microcontroller, FIG. 3 is an explanatory diagram of the operation of a conventional microcontroller, and FIG.
5 is an explanatory diagram of the operation of a conventional microcontroller, FIG. 5 is an explanatory diagram of the operation of the microcontroller according to the first embodiment of the present invention, and FIG. 6 is an explanatory diagram of the microcontroller according to the second embodiment of the present invention. FIG. 7 is a configuration diagram of a microinstruction output section of a microcontroller according to a third embodiment of the present invention;
FIG. 8 is a block diagram of a microinstruction output section of a microcontroller according to a fourth embodiment of the present invention, and FIG. 9 is a block diagram of an adder section of a fifth embodiment of the present invention. 1...Instruction register, 2...Instruction decoder, 3...
・Microinstruction output section, 4...Second register, 5...
・Incrementer, 6...first micro stack, 7
... Address selection section, 8... Second register, 9...
・Additional information modification section, 10... second micro stack,
11... Additional information selection section, 12... Third register,
13...first selector, 14...second selector. Name of agent Patent attorney Shigetaka Awano Haka 1 person 1 Zurin 9

Claims (4)

[Claims] (1) Saving is instructed in the case of an instruction that can only be executed after executing a subsequent instruction, and saving is not instructed in other cases.Input the save signal and the read address of the microinstruction, and the save signal instructs saving. a microinstruction output section that outputs a specific microinstruction when the microinstruction is to be read, and outputs the microinstruction stored in the microinstruction read address in other cases; a first register that holds the microinstruction readout address; an incrementer that inputs the microaddress output from the first register, adds +1 to it, and outputs the result; and an incrementer that inputs the microaddress outputted from the first register and the microaddress outputted from the incrementer, and the evacuation signal instructs evacuation. If the micro address is output from the first register, the first selector outputs the micro address output from the first register; otherwise, the first selector outputs the micro address output from the incrementer. If the signal instructs evacuation or the microinstruction outputted by the microinstruction output section is an evacuation instruction, the microaddress outputted by the first selector is written and saved in a stack-format storage area, and the microinstruction is used as a return instruction. In the case of , the first micro stack reads and outputs the last saved micro address, the start address of the micro program that executes the machine language instruction, the micro address output by the incrementer, and the micro stack output by the first micro stack. an address selection section that receives addresses and microaddress modification information that modifies parts of these addresses and outputs the next microaddress held by the first register; an additional information modification unit that inputs the additional information output from the second register, modifies it in a form necessary for the execution of the next microinstruction, and outputs it; and the second register. The additional information output by the second register and the additional information output by the additional information modification unit are input, and if the save signal instructs saving, the additional information output by the second register is output, and otherwise, the additional information is modified. a second selector that outputs additional information outputted by the microinstruction unit; and a second selector that receives the additional information outputted from the second selector, and receives the additional information outputted by the second selector, and the save signal instructs saving or the microinstruction outputted by the microinstruction output unit is a save instruction. If the microinstruction is a return instruction, the additional information output from the second selector is written and saved in a stack-format storage area, and if the microinstruction is a return instruction, the second microstack reads and outputs the additional information saved last; The initial value of the additional information obtained by decoding the instruction, the additional information output by the additional information modification unit, and the additional information output by the second micro stack are input, and the second register outputs the additional information held next. 1. A microcontroller comprising: an additional information selection unit that selects additional information. (2) Input the microaddress output from the first register into the incrementer and first selector, and if the save information instructs saving, output the microaddress as is; otherwise, add +1 to the microaddress. 2. The microcontroller according to claim 1, further comprising a 1/0 adder that outputs a 1/0 adder. (3) The microinstruction output section is connected to a control memory that receives the microaddress output from the first register as an input and outputs the microinstruction stored in the microaddress, and a control memory that receives the microinstruction output from the control memory as an input and outputs a save signal. 2. The micro-instruction generator according to claim 1, further comprising: a micro-instruction generating section that generates and outputs a specific micro-instruction when the control memory instructs saving, and otherwise outputs the micro-instruction outputted from the control memory as it is. Control device. (4) The micro-instruction output section is input with the micro-address output from the first register, and when the save signal instructs saving, it generates and outputs a specific micro-address; otherwise, it outputs the micro-address from the first register. 2. The microcontroller according to claim 1, wherein the microcontroller is configured using an address generation section that outputs the microaddress as it is, and a control memory that outputs the microinstruction stored in the microaddress outputted by the address generation section.