JPH02149448U - - Google Patents
Info
- Publication number
- JPH02149448U JPH02149448U JP5913489U JP5913489U JPH02149448U JP H02149448 U JPH02149448 U JP H02149448U JP 5913489 U JP5913489 U JP 5913489U JP 5913489 U JP5913489 U JP 5913489U JP H02149448 U JPH02149448 U JP H02149448U
- Authority
- JP
- Japan
- Prior art keywords
- data
- processor
- host processor
- local processor
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 8
- 230000009977 dual effect Effects 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 claims 1
- 229920002776 polycyclohexyl methacrylate Polymers 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Description
第１図は本案によるインターフエイスの構成図
、第２図は一般的に広く使われるインターフエイ
スの構成図、第３図は本案によるインターフエイ
スに対するホストプロセツサのデータ書き込み手
順を示す図、第４図は本案によるインターフエイ
ス内のローカルプロセツサのデータ転送手順を示
す図、第５図は従来のホストプロセツサのデータ
書き込み手順を示す図、第６図は従来のインター
フエイス内のローカルプロセツサのデータ転送手
順を示す図である。
１……ホストプロセツサ、２……デユアルポー
トラム、３……ローカルプロセツサ、４……デー
タ送信部、５……アドレスデコーダ、９……入出
力装置。
Fig. 1 is a block diagram of the interface according to the present invention, Fig. 2 is a block diagram of a generally widely used interface, Fig. 3 is a diagram showing the data writing procedure of the host processor to the interface according to the present scheme, and Fig. 4 is a diagram showing the procedure for writing data to the interface according to the present invention. The figure shows the data transfer procedure of the local processor in the interface according to the present invention, FIG. 5 shows the data writing procedure of the conventional host processor, and FIG. 6 shows the data transfer procedure of the local processor in the conventional interface. FIG. 3 is a diagram showing a data transfer procedure. 1... Host processor, 2... Dual port RAM, 3... Local processor, 4... Data transmitter, 5... Address decoder, 9... Input/output device.
Claims (1)
により入出力装置に転送するインターフエイスに
おいて、デユアルポートラムを用いることにより
、ホストプロセツサからボード内メモリへの直接
アクセスを可能とするとともに、データ送信エリ
アへのデータ書込時にローカルプロセツサへ割り
込み信号を発生するアドレスデコーダを用いるこ
とを特徴とするデータ転送方式。 By using a dual port RAM in the interface that transfers data from the host processor to the input/output device using the PCMA method, it is possible to directly access the on-board memory from the host processor, and also to write data to the data transmission area. A data transfer method characterized by using an address decoder that generates an interrupt signal to a local processor when a local processor is accessed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5913489U JPH02149448U (en) | 1989-05-24 | 1989-05-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5913489U JPH02149448U (en) | 1989-05-24 | 1989-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02149448U true JPH02149448U (en) | 1990-12-20 |
Family
ID=31585368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5913489U Pending JPH02149448U (en) | 1989-05-24 | 1989-05-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02149448U (en) |
-
1989
- 1989-05-24 JP JP5913489U patent/JPH02149448U/ja active Pending
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