JPH02153453A - Asynchronous data transmission device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an asynchronous data transmission device suitable for asynchronously transmitting data between two system controllers.

[Conventional technology]

When data is transmitted between two system controllers, a buffer 1 device is usually provided between these controllers in order to synchronize hardware and adjust speed lf.

In the conventional device, this buffer 1 device is provided on one side, and accesses from one controller are given priority over accesses from the other controller, thereby preparing for a collision of accesses.

[Problem to be solved by the invention]

However, in such a conventional configuration, if a write request from controller A is set to have priority over a read request from controller B in consideration of data transfer from system controller A to system controller B, if a write request comes in the middle of a read, the read The data before and after will be different, and a problem arises in that controller B cannot handle data of controller A at the same time and with the same content.

This is a big problem when transferring one set of data from system controller A to system controller B, and it becomes impossible to perform accurate data transfer.

This invention was made in view of the above circumstances, and 2.
The present invention aims to provide an asynchronous data transmission device that can perform accurate and reliable data transmission between two system controllers.

(Means for Solving the Problems) Accordingly, the present invention provides an asynchronous data transmission device that transmits data from a first system controller to a second system controller having an access time shorter than the non-access time of the first system controller. A writable first memory that temporarily stores data output from the first system controller; and a readable first memory that temporarily stores data output from the first system controller;
A second memory is provided in parallel with the second memory, in which temporary storage data of the memory is written, and this fleshed-out data is read out to the second system controller. a third memory into which output data or temporary storage data of the first memory is written and which reads out the vibration data to the second system controller; and a third memory corresponding to one write cycle of the first system controller. a first write control for simultaneously writing output data of a first system controller into one of the second and third memories and the first memory; a second write-in control for writing the data written in the first memory after the control ends to the other memory written in the first write control; The second read cycle of the system controller of
and read control means for reading data from either one of the third memories and outputting it to the second system controller.

[Effect]

In such a configuration, two memories are used to hold the data to be transferred.
a second memory, a third memory), and a first system controller on the data transmitting side and these second
．． When the first memory is arranged between the first memory and the third memory, and the first system controller writes data to the second and third memories, the data is written in two times at different times. Write. That is, during the first transfer, data is written to one of the second and third memories and the first memory, and
At the time of writing, the data in the first memory is captured in the second and third memories that were not written in the first time, and the same data is written to the second and third memories. Write data. Furthermore, when reading data from these second and third memories, the second and third memories are read out in response to a read request from the second system controller.
Data is read from the memory on the side to which writing is not being performed.

(Example) This invention will be described in detail below according to an example shown in the accompanying drawings.

FIG. 1 shows a conceptual structure of an embodiment of the present invention, and FIG. 2 shows an example of its schematic structure.

In Figures 1 and 2, system controller A
, B are provided for each industrial area, for example. In this case, the system controller (hereinafter referred to as controller) A is a mask controller that supervises and controls the industrial machine itself.
It has a normal computer configuration including a CPU, memory, etc. Further, the system controller B is used to exchange data with sensors and actuators installed in various industrial machines.

The configuration shown in FIG. 1 shows a configuration for transmitting data from controller A to controller B. Regarding the memory access period of controllers A and B, the time period Ty when controller A does not access the memory (in this case, It is assumed that the non-write time) is longer than the memory access period TB of the controller B (in this case, the read time).

That is, to be more precise, it is assumed that system A's non-access time TN^ > time required for writing after write time Td + system B's access time TB. (TNA, Td.

TB>See Figure 3).

The memory 10 is a write/read dual port RAM that can be accessed from both controllers A and B, and in this case, the most significant bit rALHJ of address rADJ
, or by changing rARHJ to H or H, the memory area is divided into two into H side and L side, thereby realizing the second and third memories in the scope of the claims. . When accessing from controller A side.

Select the H/mal area by setting rALHJ to H/L, and when accessing from controller B side, use rARH
By setting J to H/L, select H/LgJJ distribution area.

That is, in this case, the memory 1o has a so-called duplex configuration, and the H side area and the L (
As a result, exactly the same data is written every write cycle of controller A.

In this case, as mentioned above, the problem is data transfer in only one direction from controller A to controller B, so controller A only performs old reading, and controller B only performs reading 1.

There are two buffers between controller 8 and memory 10.
820 is provided. The buffer circuit 20 temporarily stores the output data DT and address AD of the controller A when data is written from the controller A to the memory 10, and thereafter writes the temporarily stored data to the H of the memory 10 in accordance with a signal from the control logic 30. It outputs to either the side area or the L [tll ffi area, and in this case, two FIFOs 20, 25
(First in first out circuit: First in First out circuit)
out) is used.

That is, the FIFO 20 stores addresses from the controller A, and the FIFO 25 stores data from the controller.

Next, before explaining the internal configuration of the control logic unit 30,
The signal input/output terminals of the memory 10 and FIFOs 20 and 25 will be explained.

C8L: Chip select from the left side of memory 10 (controller A side), C8R; WL; R; ALH: ARH: AD: DT: WF; EF; Chip select from the right side of memory 10 (controller B side), Memory 10 This is the most significant address bit of the read enable signal memory 10 of the write enable signal memory 10, and is the most significant address bit of the signal memory 10 for dividing the memory 10 into H/L areas from the left side (controller A side). , from the right side (controller B side) Signal for dividing the memory 10 into H/L areas Address signal Data Write enable signal of FIFO Data empty flag output by FIFO: (H when there is stored data in FIFO, When all stored data has been read from the FIFO, ) FR; FIFO read enable signal IN:
FIFO data input terminal OUT: FIFO data output terminal control logic section 30 is connected to control buses CB of controllers A and B as shown in FIG.
WR and the read I7 request signal RD of the controller B), the memory 106 and the FIFOs 20 and 25 are subjected to write/read control, and as shown in FIG. There is. The logic of the plurality of circuits in the control logic section 30 is all configured by hardware such as flip-flops and logic gates.

Below, before explaining each circuit configuration of the control logic section 30, the memory 10 and the FIF by the control logic section 30 will be described.
The logical configuration of write/continue output control for O20 and O25 will be briefly explained.

■First, the memory 10 is L for writing/reading.
The temporal region has a higher priority than the side chain region.

■When the write request signal WR is output from the controller A, the same data from the controller A is written to the H side area and the L side area of the memory 10 by performing dusting on the memory 10 twice at different times. Write.

During the first write (hereinafter referred to as previous write), either one of the H side area and the L9J area of the memory 10 and the F
While simultaneously writing data to IFO25,
Write the address in 20. Memory 10 H/L (I
To select which of the IIJ areas, the state of the controller B side is determined at the start of the amount of WR signal output from the controller A, and the controller B selects the H/L of the memory 10.
When reading and accessing any of the gA areas,
Writing is performed to the area on the opposite side, and if controller B is not accessing the memory 10, writing is performed to the L side area on the priority side.

During the second write (hereinafter referred to as post-write), the data written to PIFO25 during the previous write mentioned above and the F
After the previous write is completed, the address written in the IFO 20 is immediately read from the FIFOs 25 and 20, and this read data is read out from the FIFO 25 and 20 according to the address output from the FIFO 20. Write to L area.

However, when starting writing after this, controller B
When the controller B is accessing, the controller B waits until the access ends, and immediately after-writes after the access ends.

■When read request RD is output from controller B,
The state of the controller A side is determined at the start of the sending amount of this RD signal, and the controller A determines the H/Lffi of the memory 10.
When any of the areas is accessed for writing, reading is performed from the opposite area, and when controller A is not accessing, reading is performed from the priority L side area.

■When determining the state of the other controller, for example, the state of controller B is determined by the rising edge of the system clock GK, and the state of controller A is determined by the falling edge of the same system clock CK, so that judgment can be made at the same time. We are trying to prevent this.

The above is an outline of the logic of the control logic unit 30. Hereinafter, the operation of the control logic unit 30 shown in FIG. 1 will be briefly explained according to the time chart shown in FIG.

In Figure 3, (a) is from controller A to memory 1.
(b) shows the read state of controller B, (C) shows the state of writing to FIFO 20, 2 from controller A.
(d) shows the post-write state, and in each signal, L is active. Further, 0 0 added above each signal indicates the H/LiW area of the memory 10.

At time tolc, since controller B is accessing the L side fr4wl of the memory 10, the H side area is selected as the access target from the controller A side, and as a result, during the period from time t○ to time t2, Controller A
data is allocated to the H side area of the memory 10, and the data and address of the controller A are stored in the FIFO 25,
Pre-write processing is performed at 20. Note that in the read processing of controller B from time t1 to t3, since the H side area of the memory 1o is occupied by controller A at time t1, controller B
The L side area is selected as the access target.

Next, when the previous write to the controller is completed, 11 t
In No. 2, the L-side area where the rear writing is to be performed is followed by controller B six times.

Therefore, in the control logic unit 30, the controller B
Waits until the access of
The after-write starts from 3) a after-write takes time Td.

Next, during the access period of controller B from time t4 to time t5, since both the H and L areas of the memory 10 are empty, the left side area set as the priority area is selected.

Furthermore, since both the H and L areas of the memory 10 are empty at the subsequent time t6 when controller A starts accessing, controller AG performs pre-write to the priority side area. Of course, at the same time, the data and address of controllers 0-A are transferred to FIFO2.
5.20 was passed.

At time t7 when controller A's prewrite is completed, controller B is not accessing the H-side area to which postwrite is to be performed.

Therefore, in this case, post-writing is performed immediately from time t7 without any waiting time. Note that at time t8, the HII ffi area of the memory 10 is being rewritten, so the controller B uses L as a read target.
The side area is selected.

Next, each circuit configuration within the control logic section 30 will be explained with reference to FIG. In FIG. 2, the system clock CK is input to various places, but only important points show the input state, and other parts are omitted.

Write request signal WR of controller A (Fig. 4(a))
is input to the previous write section generating circuit 31 and the gate 32. Note that the pulse period of the system clock GK mentioned above is sufficiently shorter than the pulse width of the write request signal WR.

The previous write section generation circuit 31 is composed of a one-shot multivibrator circuit, a flip 70 tube, etc., and takes in the store request signal WR at the falling edge of the system clock GK, and then generates a PPCW signal that maintains the L state for a predetermined time TA. shape! fc+,... is output (Fig. 4(b)). This PPCW signal number is a flag signal indicating that controller A is in the process of writing (that is, in the previous write) when the signal level is 1.

The gate 32 receives the output of the PPCW signal delayed for a predetermined time by the delay circuit 50 and the inverted outputs of the WR signal, and inputs the NAND output to the WF terminal of the FIFO 20°2Z (Fig. 4(C)). ).

When the input to the WF terminal of FIFO20, 25G is L,
Address signals and data signals output from controller A are written into the storage areas of the FIFOs 20 and 25, respectively.

The pre-write end detection circuit 33 outputs a WRED signal indicating the end of the pre-write by detecting the rising of the PPCW signal from L to H.

The EF signal, WRE 0m, and feedback signal from the FIFO 20 are input to the PFD generation circuit 34, which is internally comprised of a plurality of logic gates, flip-flops, and the like. EF (as mentioned above, the signal (h) in FIG. 4 is the empty flag of the FIFO 20, and is in the H state while the above-mentioned front write and back write are being performed.) The PFD generation circuit 34 outputs the WRED signal. A PFD signal is formed that falls at the rising edge of the ppcw signal, that is, the rising edge of the ppcw signal, and rises at the falling edge of the EF signal.

That is, the PF[) signal becomes L from the end of the previous write to the end of the second write. Note that this PFD signal is latched at the falling edge of clock CK.

The lead section generation circuit 35 is a flip-flop,
The read request signal RD output from the controller B is latched at the rising edge of the clock, and the read period signal C0RT of the controller B is output (FIG. 4(f)). This C
The output of the 0RT signal is held at L while controller B is reading. This C0RT signal is
It is input to the C8R terminal and R terminal of. therefore,
Memory 1 is always
Storage data is read from either of the H/L side areas of 0. That is, there is no waiting time for reading.

At the time of reading, which of the H and L areas is selected is determined by the ARH signal (
4(n)). The logical configuration of this system A side state determination circuit 38 will be described in detail later, but its outline will be briefly described. That is, this judgment circuit 38
The truth table is shown in Table 1 below.

In Table 1, for the signal A 10 H, when the ppcw signal is L, the truth table is as shown in Table 2 below.

Table 2 C8L, Alt-1 shows the state when C0RT falls, and when the ARH signal is H, the H side area of the memory 10 is selected, and when it is L, the L side chain area of the memory 10 is selected. selected.

The system B side state determination circuit 36 determines whether the controller B
The access state of the controller A side is determined at the time when the PPCW signal falls to L, and in response to this determination, the controller A side determines which area (H/LIt area) of the memory 1o to select, and indicates this. Outputs signal A10H (Fig. 4 (
J)).

C0RT and ARH are in the state when PPCW falls, that is, as mentioned above, in memory 10, priority is given to the L side chain area, and therefore, C0RT and ARH are set at the start of the previous write.
When the signal is Hl, that is, controller B is not accessing, the A10H signal becomes low corresponding to the priority area (L area) of the memory 10, and when the C0RT signal is Ll, that is, controller B is accessing, at the start of the previous write, The A10H signal is the inverse of the AR)I signal and selects an area opposite to the area being accessed by controller B.

The selector 37 switches between the AlOH signal and its inverted signal according to the states of the PPCW signal and the PFD signal.
The output ALH includes the signal A1 when the PPCW signal is L (during front write).
When the non-inverted output of 0H is selected and the PFD signal is
(from the end of the front write to the end of the rear write) is signal A10.
The inverted output of H is selected, and the PPCW signal and PF
When the n signal is H, Lffi is selected corresponding to the priority area of the memory 10. In other words, the selector 37 is used to select an area on the opposite side to the area during the front write during the rear write. ALH output from this selector 37
The signal is input to the ALI (terminal) that selects the H side region and L side chain region of the memory 10.

The after-write wait condition generation circuit 39 generates a part of the condition under which the after-write from the FIFO 20° 25 to the memory 10 is made to wait due to the controller B's access to the memory 10.
H@ and AI Of (signal as input signal, PW
The T@ number is output (Fig. 4 (j)). The PWT signal becomes active when the wait conditions shown in Table 3 below are satisfied.

In Table 3, that is, in the above table, the inverted signal of A10H represents the rear write memory area, so A10 and ARI-1
<access area on the controller B side) and when the C0RT signal is L (controller B is accessing), it is necessary to make the post-write wait, and the PWT48@ is set to L.

This PWT signal is input to the gate 40, ANDed with the inverted signal of the PFD@ signal, and after being further inverted, the PF
It is output as a DE signal (FIG. 4(k)). That is, the gate 40 forms and outputs a PFDE signal that only occurs during the post-write period. Furthermore, this P
The FDE signal is also latched at the falling edge of clock GK.

This PFDE signal is input to gates 41, 43, and 44. The gate 41 takes the NOR between the inverted signal of the PFDE signal and the inverted signal of the PPCW signal, and inputs the NOR output C8L to the C8L terminal of the memory 10. That is, the gate 41 determines that during pre-write (PPCW), ! :
After writing vf (PFDE), the C8L signal becomes L, and at this time, chips in the memory 10 are selected from the left side.

The C8L signal is also input to the system A side state determination circuit 38. The A-side state determination circuit 38 receives the input C8L.
The access state on the controller A side is determined based on the signal and the ALH signal at the time when the C0RT signal falls;
In response to this determination, the controller B side determines which area of the memory 10 <H/L area) and outputs a signal ARH indicating the selection result (see FIG. 4).
n)). The truth table is shown in Table 2. Note that, like the A L H signal, when the ARH signal is H, the H side region of the memory 10 is selected, and when it is L, the L temporal region of the memory 10 is selected.

Pulse signals whose phases are slightly shifted from the pulse generator 42 are input to the gates 43 and 44, respectively, and the passage of the pulse signals is controlled by the PFDE signal input to the other terminal of each gate 43 and 44.

Shutdown is toggled. That is, when the PFDE signal is L, the pulse output from the pulse generator 42 is output from each gate 43,44.

The pulse signal passing through the gate 43 is sent to FIFOs 20 and 25.
is input to the FR terminal of. Therefore, FIFO20,
From 25, the address and data stored during the previous write are output in accordance with the output pulse of the pulse generator when the PFDE signal becomes L. The address output from the FIFO 20 is input to the AD terminal of the memory 10,
DT of memory 10 is applied to the data output from FIF025.
input to the terminal.

On the other hand, the pulse signal that has passed through the gate 44 is input to the gate 45. The gate 45 takes the NOR of the output of the gate 32 and the output of the gate 44 and inputs the result to the WL terminal of the memory 10. That is, the gate 45 outputs the output of the gate 32 (W during the period in which the PPCW signal is low) indicating that the previous write is in progress.
By taking the NOR between the R times signal (during front write) and the output of the gate 44 indicating that the back write is in progress (the output of the pulse generator during the period when the PFDE signal is on), the pulse train necessary for the front write and rear write is obtained. is input to the WL terminal of the memory 10.

In this case, the rear light is the FIF of the hardware configuration.
Since the output is controlled from O20, 25, the front light <
The length (PFDE) is extremely shorter than p p Q W), so pulses are generated so that the same number of pulse signals as the ■π signal are output during the period when this PFDE signal is L. The frequency of the output pulse signal of the device 42 is determined.

The above is the configuration of the control logic section 30, and its operation will be explained below with reference to the time chart shown in FIG.

At time t1, the first WR double signal controller A
(Fig. 4(a)). The previous write section generation circuit 31 generates this first WR multiplication signal and uses the state as a clock G.
It is triggered at the falling edge of K, and then is outputted via gate 32, which maintains this state for a predetermined period of time TA. WF and WL are input to the WL terminal of the memory 10 (FIGS. 4(c) and 4(e)), respectively, and are write enable terminals. At the same time (time t
1) The PPCW signal is passed through the gate 41 to the C of the memory 1o.
When the 8L terminal (FIG. 4(d)) is input, chip selection from the left side becomes possible. Furthermore, at the same time, the system B side state determination circuit 36 determines the state of the controller B side based on the states of the CORT signal and ARH signal at the time when the PPCW signal falls (time t1), and based on this determination result. A signal indicating which H/L area of the memory 10 is selected is output. In this case, since the CORT signal is H and the ARH signal is high at time t1, A10 is set so that the L side chain region on the priority side is selected.
The H signal becomes L (see Table 2). This AlOH signal is input to the ALH terminal of the memory 10 via the selector 37. As a result, during the period from time t1 to time t7 when the PPCW signal is active, the data of controller A is written to the L side chain area of the memory 10 in synchronization with the WR low signal of system controller A. The address is written to FI FO20, and then controller A
A pre-write process is executed in which data is written to the FIFO 25.

Note that during this pre-write process, controller B
is being accessed (read), and in the system A side state determination circuit 38, the time t2. t3. At t4°ts, te), the access state on the controller A side is determined, and based on this determination result, the area of the memory 10 to be accessed by the controller B is selected. In this case, since controller A has selected the L side chain area of the memory 10 during the previous write period, the access target of controller B during this previous write period is, as can be seen from the ARH signal, This is the H side region (see Table 1).

Thereafter, when the pre-write process is completed, this is detected as a rising edge of the PPCW signal by the song write end detection circuit 33, and the circuit 33 outputs the WRED signal (time t
7).

Due to this WRED signal, the PFD signal output from the PFD generation circuit 34 falls to [[] at time t7. As described above, the selector 37 outputs the inverted signal of the AI OH signal while the PFD signal is L, so at time t7
During the period from t9 to t9, the ALH signal becomes H.

Also, in this case, memory 1 to which the post-write is to be performed
The waiting time (Tc
) exists. Therefore, due to the configuration of the post-write waiting condition generation circuit 39 and the gate 40, the post-write is started after the waiting time TC exists. That is, at time 0, the PFDEM signal falls to L due to the rising edge of the QORT signal, and subsequently, at time t9, the PFDE signal becomes E
It rises to H due to the rise of the PFD signal due to the rise of the F signal. The period from time t8 to time t9 is the post-write period, and during this period, the output pulses of the pulse generator 42 are inputted to the FR terminals (read enable) of the FIFOs 20 and 25 by the PFDF signal (see FIG. 4). d)) The output pulse of the same pulse light generator 42 is input to the WL terminal (write enable) of the memory 10.Furthermore, the C8L terminal of the memory 10 is also in the chip select state by the PFDEI signal.

Therefore, during this period from time t8 to time t9, FIF
The output of the FIFO 25, that is, the address signal output from the controller A during the previous write, is input to the AD terminal of the memory 10, and the output of the FIFO 25, that is, the data output from the controller A during the previous write, is input to the memory 10. is input to the DT terminal of the
Since the terminal is set to H, the result is that the memory 10 is set to H (
The data output from controller A during the previous write will be written into the Ill area. As a result of subsequent writing, the stored contents of the L side chain area and the H side area of the memory 10 become exactly the same. Incidentally, FIG. 6 shows an example of an accurate time chart of PFDE, FR, and WL in the post-write period.

Figure 5 shows the access cycle (PPC) from controller A.
W) and access cycle from controller B (CORT)
4, and its basic operation is the same as that shown in FIG. 4, so the explanation will be omitted.

In this figure 5 as well, after some light weight period T
c exists.

In the above embodiment, the memory 10 is divided into two parts based on the most significant bit address, but as a memory duplication configuration, the memory 10 can be divided into two parts using bits other than the most significant bit.
It may also be divided, and furthermore, a memory made up of two different chips may be used. Further, the logical configuration of the control logic section 30 may be any other logical configuration as long as it achieves functions equivalent to these.

Furthermore, instead of a FIFO as a buffer circuit, an ordinary set of seven lip-flops may be used.

[Effects of the Invention] As explained above, according to the present invention, in data transmission between system controllers having different memory access periods, memories are arranged in duplicate between these data transmission paths, and one system accesses these memories. When writing data from the controller, the writing is done in two steps at different times, and when reading access to these memories from the other system controller, the data is written from the memory on the side that is not being used. Since the data is read from the system controller, the data is not interrupted in the middle of the access cycle of each system controller.This allows the system controller on the receiving side to receive data at the same time and with the same content from the controller on the sending side, which prevents errors. Accurate data transmission can be achieved without

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of the internal circuit configuration of the embodiment device, and FIG. 3 is a time chart conceptually showing the operation of the embodiment device. FIGS. 4 to 6 are time charts for explaining more detailed operations of the embodiment apparatus, respectively. A, B...System controller, 10...Memory (dual port memory), 20.25...Buffer circuit (FIFO), 30...Control logic section.

Claims (4)

[Claims] (1) In an asynchronous data transmission device that transmits data from a first system controller to a second system controller having an access time shorter than the non-access time of the first system controller, the data is output from the first system controller. a first memory that is readable and writable for temporarily storing data; and output data of the first system controller or temporary storage data of the first memory is written, and the written data is transmitted to the second system controller. A second memory is provided in parallel with the second memory for reading data to the first system controller, and output data of the first system controller or temporary storage data of the first memory is written, and the written data is written to the second memory. a third memory for reading out data to a second system controller; and a third memory for reading output data from the first system controller to one of the second and third memories in response to one write cycle of the first system controller. a first write control to simultaneously write to one memory and the first memory; and after the end of this first write control, the data written to the first memory is written by the first write control; write control means for performing second write control for writing to the other of the second or third memory; An asynchronous data transmission device comprising read control means for reading data from either one and outputting it to a second system controller. (2) The second and third memories have a predetermined priority set in advance with respect to access from the first and second system controllers, and the write control means receives access from the first system controller. a first determining means for determining the state of access to the second and third memories by the second system controller at the start of a write request; and based on the output of the first determining means and the priority order. a first selecting means for selecting a memory which is not accessed by the second system controller from among the second and third memories; A memory corresponding to the selection result of the selection means and a first memory to the first memory.
a first writing unit that performs the first write control to simultaneously write output data of the system controller; and a first write unit that performs the first write control to simultaneously write output data of the system controller; a second determining means for determining an access state; and writing data stored in the first memory into the other memory selected by the first selecting means in accordance with a determination result of the second determining means. a second write unit that performs a second write control, and the read control unit performs read control from the first system controller or the first memory at the start of a read request from the second system controller. a third determining means for determining the state of access to the second and third memories by writing; and a third determining means for determining the state of access to the second and third memories by writing; and a second selection means for selecting a memory not accessed by the first system controller, and a memory corresponding to the selection result of the second selection means in response to a read request from the second system controller. The asynchronous data transmission device according to claim 1, further comprising reading means for reading the stored data and outputting it to the second system controller. (3) The second writing means causes the second system controller to write data stored in the first memory of the second and third memories from the second determining means to a memory to which data is to be written. Claim 1, further comprising a standby means for causing the second write control to wait until the access by the second system controller is completed when a determination result indicating that the access is in progress is output.
2) The asynchronous data transmission device described above. (4) The asynchronous data transmission device according to claim (2), wherein the first and second determining means are configured such that their determining times are always different.