JPH0217976B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for controlling received data by selecting an internal clock having an optimal phase relationship with the received data from among a plurality of internal clocks having different phases. It is an object of the present invention to provide a phase synchronization device that can obtain an output clock having an optimal phase.

Conventionally, in order to obtain an output clock with an optimal phase relationship with respect to received data, an original clock with a frequency that is an integral multiple of the output clock is used, and when the received data triggers, counting is started using the original clock, and a trigger is issued at an appropriate point. Although this method used to generate an output clock with an optimal phase, it had the disadvantage that the circuit was complicated because it was a counter-based device.

The present invention aims to provide a phase synchronization device that eliminates the above-mentioned drawbacks, and one embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the phase synchronization device of the present invention. 3 is a discrimination circuit, 4 is an oscillator, 5 is a frequency divider, and 6 is a switching circuit. The output 101 of the first timer 1 triggered by the rising edge of the received data 100 shown in FIG.
and the output 20 of the second timer 2 which is triggered at the same time.
1 changes simultaneously by a trigger and returns to the original state after each set time. In other words, the two timers have a function of delaying the trigger information by the respective set times, and the outputs of the two timers have different states during the difference in the set times, that is, the delay times. The discrimination circuit 3 is switched to the switching circuit 6 during the above period.
It is determined whether the output clock 601 rises or not, and if it does not rise, the switching pulse 30 is sent to the switching circuit 6.
1, otherwise the switching pulse 301 is not output. In this embodiment, the frequency divider 5 divides the output 401 of the oscillator 4, which is oscillating at twice the frequency of the output clock, by two to generate internal clocks 501 to 504 having four different phases, and the switching circuit 6 selects one of the internal clocks 501 to 504 from the frequency divider 5 and sends it to the discrimination circuit 3 as an output clock 601, and upon receiving the switching pulse 301 from the discrimination circuit 3, changes the output clock to be selected; An internal clock of another phase is sent as output clock 601.

FIG. 2 is a time chart showing the waveforms of each part, and shows how the output clock is selected for received data. The process of obtaining an output clock having an optimal phase relationship with received data will now be explained. Assuming that the received data 100 is an NRZ signal, it is considered that the output clock having the optimum phase relationship with respect to it rises around 1/2 period of the received data 100 from the change point of the received data 100. The setting time of the first timer 1 is shorter than 1/2 period of the received data 100, and
The set time of timer 2 is longer than 1/2 cycle, and the difference between the two is longer than 1/4 cycle of received data 100,
The internal clock rising during this difference period is at least 1
There is one clock, and the length is determined so that this clock is considered suitable for the received data 100.

Triggered by the rising edge of the received data 100, the first timer output 101 and the second timer output 201 become "1" for a set time. In other words, the rising edge information of the received data 100 is delayed by the first timer 1 to the falling edge of the first timer output 101, and at the same time
The falling edge of the second timer output 201 is delayed by the timer 2. If a is a value that becomes "1" when 101 is "0" and 201 is "1", the discrimination circuit 3 outputs a switching pulse 301 if the output clock 601 does not rise when a is "1". do. The phase relationship of the internal clocks 501 to 504, which are obtained by dividing the output 401 of the oscillator 4 by the frequency divider 5, is as shown in FIG. It is assumed that the output clock 601 is sequentially switched and output as the output clock 601. In the example time chart of FIG. 2, when a is "1" for the first time, the output clock 6
01 does not rise, the switching pulse 301 is generated, and the output clock 601 is switched from 501 to 502. However, since the output clock 601 does not rise even when a is "1" for the second time, it is the same as before. A switching pulse 301 is generated and output clock 601 is switched from 502 to 503. After this, the output clock 601 always rises when a is "1", so the switching pulse 301 is not generated, and an output clock whose phase relationship is stably maintained can be obtained. When the phase of received data 100 changes, the above operation is performed and an optimal output clock is obtained.

As described above, the present invention includes an internal clock generating section that generates a plurality of internal clocks with different phases at a desired synchronization frequency, a first delay section that delays the phase of a change point of transmitted data for a certain period of time, and The state of the internal clock is determined between a second delay section that delays the clock by a time different from the delay time of the first delay section, and a phase difference between the points of change in the output of the first delay section and the output of the second delay section. It consists of a logic condition determination section that makes a decision based on a predetermined logic condition, and an internal clock selection section that selects and outputs an internal clock with a phase that satisfies the logic condition, and selects one internal clock that satisfies the logic condition. This is a phase synchronization device that is characterized by obtaining an output clock having a desired phase relationship with respect to received data.By setting the setting times of the two delay sections to appropriate values, it can be achieved with a simple circuit configuration. A stable clock having an optimal phase relationship with respect to received data can be obtained.

In the present invention, since the phases of the received data and the internal clock are directly compared, there is no need to extract the clock for phase comparison from the received data, and it is possible to detect the phase difference by averaging over a certain amount of time. Since it is determined by logical conditions, the phase state can be determined immediately. For example, if there are internal clocks with n phases (n is an integer), the internal clock with the optimal phase can be selected with a maximum of (n-1) decisions. Completed,
The practical effect is that the transition to the optimal state is rapid.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a phase synchronization device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the device. 1...First one-shot timer circuit (first timer), 2...Second one-shot timer circuit (second timer)
timer), 3...discrimination circuit, 4...oscillator, 5...
... Frequency divider, 6... Switching circuit, 100... Received data, 101... First one-shot timer circuit output, 201... Second one-shot timer circuit, 3
01... Switching pulse, 401... Oscillator output,
501-504...Internal clock of frequency divider, 60
1...Output clock.

Claims (1)

[Claims] 1. An internal clock generation section that generates a plurality of internal clocks with different phases at a desired synchronization frequency, a first delay section that delays the phase of a change point of received data for a certain period of time, and a delay section that delays the phase by the first delay section. Logic that determines the state of the internal clock based on a predetermined logical condition between a second delay section that delays the clock by a time different from the second delay section, and a phase difference between the change points in the output of the first delay section and the output of the second delay section. It consists of a condition determination section and an internal clock selection section that selects and outputs an internal clock with a phase that satisfies the logical condition, and selects one internal clock that satisfies the logical condition to determine the desired state for the received data. A phase synchronization device characterized in that it obtains an output clock having a phase relationship of: