JPH0217996U - - Google Patents
Info
- Publication number
- JPH0217996U JPH0217996U JP1988096981U JP9698188U JPH0217996U JP H0217996 U JPH0217996 U JP H0217996U JP 1988096981 U JP1988096981 U JP 1988096981U JP 9698188 U JP9698188 U JP 9698188U JP H0217996 U JPH0217996 U JP H0217996U
- Authority
- JP
- Japan
- Prior art keywords
- analog
- setting device
- quantity setting
- clock pulses
- electrical quantities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Velocity Or Acceleration (AREA)
- Control Of Electric Motors In General (AREA)
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の一実施例によるアナログ量
設定装置を示す回路図、第２図は従来のアナログ
量設定装置を示す回路図である。
図において、６はクロツクパルス発生回路、８
はアツプダウンカウンタ、９はＤ／Ａ変換器、１
１は上限値認識用ＮＡＮＤ素子、１２は下限値認
識用ＯＲ素子である。なお、図中、同一符号は同
一または相当部分を示す。
FIG. 1 is a circuit diagram showing an analog quantity setting device according to an embodiment of this invention, and FIG. 2 is a circuit diagram showing a conventional analog quantity setting device. In the figure, 6 is a clock pulse generation circuit, and 8 is a clock pulse generation circuit.
is an up-down counter, 9 is a D/A converter, 1
1 is a NAND element for recognizing an upper limit value, and 12 is an OR element for recognizing a lower limit value. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
値で設定変更するアツプダウンカウンタと、クロ
ツクパルスを生成する発生回路と、デイジタルで
設定された電気量をアナログ値に変換するデイジ
タル／アナログ変換器とを備えたアナログ量設定
装置において、設定値認識回路を設けたことを特
徴とするアナログ量設定装置。 An analog device that is equipped with an up-down counter that inputs electrical quantities as clock pulses and changes settings using digital values, a generation circuit that generates clock pulses, and a digital/analog converter that converts digitally set electrical quantities into analog values. An analog quantity setting device characterized in that the quantity setting device is provided with a set value recognition circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988096981U JPH0217996U (en) | 1988-07-22 | 1988-07-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988096981U JPH0217996U (en) | 1988-07-22 | 1988-07-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0217996U true JPH0217996U (en) | 1990-02-06 |
Family
ID=31322157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988096981U Pending JPH0217996U (en) | 1988-07-22 | 1988-07-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0217996U (en) |
-
1988
- 1988-07-22 JP JP1988096981U patent/JPH0217996U/ja active Pending