JPH0218054A - Multiplexer circuit - Google Patents

Abstract

PURPOSE: To provide a multiplexer circuit having necessity for handling only comparatively low electric power by enabling discharge of a capacitor connected to one electrical path to be caused when a first and a second switching members of one electrical path are respectively opened and closed. CONSTITUTION: Electrical paths 113-117 respectively containing the collector/ emitter paths of n-p-n bipolar transistor devices 133-137 are provided between terminals 63-67 and a path 103. The paste electrical paths of these devices respectively contain field effect devices 143-147 and an internal generation logical signal which makes these devices conductive is impressed to the gate electrodes thereof. The collector/emitter paths of the devices 133-137 are shunted in the respective field effect devices 153-157 in which gate electrodes are connected to the gate electrodes of the devices 143-147. Accordingly, these devices are made conductive by the same logical signal actuating the devices 163-147. The devices 153-157 themselves are respectively shunted in the diodes 163-167 and the discharge path of a capacitor is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multiplexer circuit for operating selected devices of each group of a series of capacitor-operated devices in successive operating phases. Regarding.

PRIOR ART AND PROBLEM TO BE SOLVED BY THE INVENTION One application of such a multiplexer circuit is to have a pulsed area deposition device, e.g. a multiple channel array, from which droplets are ejected and are arranged in groups, and channels from each group are selected for droplet printing in successive operating phases of a multiplexer circuit. Known forms of pulsed ink drop jet printers, so-called "call for extraction" printers, require substantial circuitry to handle the operating current, which poses a risk of burnout.

A primary object of the present invention is to provide a multi-breather circuit for such applications that handles only relatively low power and requires only 5. Additionally, in known forms of pulsed ink drop jet printers, the switching of the substantial operating current causes disturbing geo-frequency disturbances. It is therefore a second object of the present invention to minimize such disturbances.

SUMMARY OF THE INVENTION The present invention is a multiplexer circuit for operating selected devices of each group of devices in a series of capacitively actuated devices in successive operating phases, connecting each device. a series of parallel connected circuits configured such that the circuits are configured to be connected in parallel with the signal generator, and the circuits of the combined device and the circuit of the combined device are connected in parallel with the signal generator; two capacitors of each device connected between the respective electrical circuits on the opposite side of the electrical circuit, and a configuration in which the two capacitors of each device are arranged in each electrical circuit of the combined device and are closed by respective logic signals applied thereto; - the first and second switching members of the electrical circuit are closed and opened, respectively; Charging of the capacitor connected to the electrical circuit occurs when the second switching member is opened and closed, respectively, and thereafter when the first and second switching members of the electrical circuit are opened and closed, respectively. A multiplexer circuit is provided, characterized in that a capacitor connected to the electrical circuit is discharged.

Suitably, a diode device is connected across the second switching member of each circuit, and a capacitor discharge circuit is connected between the circuit to which the diode is connected and the circuit on the respective opposite side. providing.

Preferably, the first and second switching members are provided on a silicon chip integrated circuit, and the switching members comprise transistor switches. Suitably, the transistor element comprises a field effect transistor.

In one aspect of the multiplexer circuit according to the invention, the second switching member of each electrical path has first and second switching components, and the first switching component connects the electrical path including the second switching member. a bypass in parallel with a second switching component that utilizes a first switching member of the electrical path on the opposite side of the electrical path including the second switching member when charging a capacitor connected between the electrical path and the electrical path on the opposite side thereof; providing an electrical path, while after charging a capacitor connected to the electrical path including the second switching component, the second switching component connects the capacitor using a first switching member included in the same electrical path as the second switching component; Provides a conductive path.

Preferably, the first and second switching members are mounted on a silicon chip integrated circuit, the first switching member comprises a field effect transistor, and the first and second switching components of the second switching member comprise a field effect transistor and a second switching member. Bipolar transistor (field effect transistor) that controls conductivity with field effect transistor
affectfra/le5iacor contr
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α bipolar franaimtor).

Preferably, in each operating phase, the capacitors of the devices selected to operate are charged with an initial portion of the voltage waveform supplied by the signal generator, and then during the next period of said waveform, the capacitors of the devices selected to operate are charged by the signal generator. Discharge of the capacitor that was disconnected from the circuit and then charged occurs. Preferably, the signal generator and the parallel circuit and its first and second switching members are formed on a silicon chip integrated circuit.

According to a feature of the invention, the actuation of each selected device must produce substantially the same effect, and the actuation of any device is influenced by the actuation or inaction of the device opposite it. It is important to activate each selected device according to the activation or non-activation of the device adjacent to the selected device.For this purpose, the logic signal applying member is used to activate the selected device. a capacitor of each device selected for a period of time depending on the activation or inactivation state of a device adjacent to each of the selected devices;
The configuration is such that a signal is applied to the first and second switching members to enable charging.

The present invention further provides a multi-M flow array electrical pulse width deposition apparatus for depositing droplets onto a surface, the apparatus comprising: a sub-deposition head formed from an electrically active material; multiple channels arranged in multiple groups for the liquid to be stored, nozzles communicating with each channel, longitudinal side walls each serving to separate one channel from the next, and an electrically actuated member for effecting lateral displacement of the longitudinal sidewalls in opposite directions, the electrically actuable member comprising electrodes in each channel on respective opposing faces of the longitudinal channel sidewalls; a conductive member connecting the electrodes of each channel;
The electrodes form a series capacitor, each capacitor comprising an electrode on the sidewall of the longitudinal channel and an electrode on the opposite side thereof, and a multiplexer circuit for carrying out the actuation of the sidewalls in successive phases, said circuit having a series of parallel electrical circuits), said capacitor being connected between each successive circuit of said electrical circuits; a signal generator connected to both ends of the parallel electrical circuit, first and second switching members disposed in each of the electrical circuits, and conduction of the first and second switching members; - the first and second switching members of the electrical circuits are closed and opened, respectively, and the first switching member of each electrical circuit on the opposite side of the electrical circuit is
Charging of a capacitor connected to the electrical circuit occurs when the first and second switching members of the electrical circuit are opened and closed, respectively, and thereafter, when the first and second switching members of the electrical circuit are opened and closed, respectively. This is an electric pulse attachment device characterized by the discharge of a capacitor.

In the pulse margin deposition device according to the present invention, channel wall compliance (deflection), i.e., crosstalk due to the effect of pressure present in adjacent channels on the working channel, is eliminated in accordance with an important feature of the invention. can be compensated for. To achieve this compensation, the logic signal applying member is connected to the selected channel capacitor and the selected channel capacitor is connected to each first circuit for charging the selected channel capacitor of each of the parallel circuits.
and a signal is applied to the second switching member for a period of time to provide a voltage level corresponding to the selected or non-selected state of the adjacent flow path of the group including the selected flow path.

Preferably, when charging the capacitor, the signal generator:
It is configured to apply a voltage signal that increases relatively slowly to the capacitor in the selected flow path, and the logic signal applying member applies the voltage signal to the capacitor in the selected flow path when a predetermined charging voltage is reached. The signal generator is configured to disconnect the signal generator from the capacitor of the selected flow path and actuate the switching member at intervals to effect rapid discharge of the charged capacitor. The longitudinal sidewalls are displaced outwardly relatively gradually, and the channel walls are adapted to return quickly upon discharge of the capacitor.

EXAMPLES The invention will now be described by way of example with reference to the attached schematic drawings.

Similar parts in the figures have been given the same reference numerals.

FIG. 1 shows a modular portion 10 of an inkjet printhead 12 in which multiple, closely adjacent, extraction requesting ink drop ejectors are arranged side by side. The ejector is filled with ink and piezoelectric shear mode wall actuators 30-39. It consists of parallel extending channels 20-28 separated by, for example, those disclosed in co-pending European Patent Application No. 88300146.3, the contents of which are hereby incorporated by reference.

The ink channels 20-28 have electrodes 40-4 covering the walls of each channel.
8, which serves as the actuation electrode for the wall actuator and, together with the wall actuator, effectively forms a capacitor 50-58. t#L is connected via tracks 70-78 to terminals 60-68 of a silicon chip integrated circuit, which will be described later.

As explained in the aforementioned co-pending European patent application,
The ink ejectors are divided into two groups of odd and even numbered channels, respectively, and selected channels of the odd and even numbered groups are activated in alternating cycles. In a typical cycle,
The operation is carried out by holding the electrodes of one group (eg, even numbered channels) and applying a voltage waveform from the printing of the odd numbered channels to these channels.

A typical multiplexer drive circuit is shown in FIG. In the figure, an internal bus 10 is located in a silicon chip integrated circuit 101.
2 and 103, bus 102 is connected to the positive output terminal of the signal generator, and bus 103 is connected to the negative output terminal of the signal generator held at ground voltage. connected to the output terminal. Between buses 102 and 103 there are parallel electrical paths, each associated with an actuator channel, of which only electrical paths 113-117 are shown, including terminals 63-117, respectively. Contains 67.

Between bus 102 and terminals 63 to 67, field effect transistors (devices) are placed in electrical circuits 113 to 117, respectively.
123 to 127 are connected, and as will be described later, each (transistor) gate) 1! [An internally generated logic signal can be applied to the poles that makes the device conductive.

Between terminals 63-67 and bus 103 are electrical paths 113-117 containing the collector-emitter paths of n-p-n bipolar transistor devices 133-137, respectively.

The pace circuits of these devices each include a field effect device 143-147 to the gate electrode of which an internally generated logic signal can be applied that causes these devices to become conductive. The collector emitter paths of devices 133-137 are connected to the respective electrode effect devices 153 whose gate electrodes are connected to the gate electrodes of devices 143-147.
are shunted at 157, thus making these devices conductive with the same logic signal that activates devices 143-147. Devices 153-157 are themselves shunted with diodes 163-167, respectively, which form capacitor discharge paths as described below.

Transistors 123-127, 143-147 and 15
Logic signals for implementing and terminating conduction of 3-157 are provided by registers 173-177 of logic block 178, which are provided with print pattern data on line 179 and relatively high frequency clock pulses on line 180. , line 180 is also connected to a signal generator 100, to which is also connected a clock line 181, which supplies relatively low frequency clock pulses.

The data stream provided on line 179 is applied to each chip of the printhead in an N bit-print pattern (N
is the number of channels to which the chip is connected). The N bit determines which of the even numbered channels should be activated during the first cycle and which of the odd numbered channels should be activated during the next cycle. The N-bit data stream also includes a subset (W) of data regarding the print status of the same group of channels that are selected for activation, on the opposite side (adjacent) of the channels selected for activation. There is. Data set n may be a 4-bit word (in which case it gives the print status of two channels (destinations) in the same group as the selected channel, on either side of each channel selected to operate. When the data set is in the form of 6-bit words, it provides the print status of three channels on either side of each channel to be activated.

After the print line has finished printing and before the next pulse to the signal generator 100 is applied on line 181, data N with subset n is sent to registers 173-177 by the clock pulse on line 180, preferably about Loaded with speed set by 10MHz clock pulse,
and dataset n is (not shown) RUAI
The digital signals determined by the data set are sent to the index table of registers 173-177.
This signal is stored in a register and used to provide a count of pulses on line 180 that determines the charge level of the capacitor in each active flow path.

The voltage cycles applied by signal generator 100 between buses 102 and 103 are initiated by a pulse on clock line 181, and when one such cycle begins, the data stored in registers 171-177 is switched on. One of the channels having transistors 123-127 switched off and transistors 143-147 switched off is selected for printing the channel, charging of the capacitor of the selected channel begins and the capacitor transistor 12 of the selected flow path when the voltage level of transistor 12 of the selected flow path reaches a value determined by a digital signal stored in registers 173-179 and supplied from the above-mentioned index table.
It ends with the switch off at 3-127. The registers of each of the end channels of the modière that form the print head are easily understood.

A set of bits 9 is received from the ROM, which provides the printed state of the adjacent channel across the intimate area of the module in which the terminal channel of interest is located and the adjacent module. The integrated circuit of FIG. 2 has a bi-Cfnos structure.

FIG. 4 shows the waveforms provided by signal generator 100 to energize actuators 30-39 during successive phases of the two-phase multiplexer circuit of FIG. This waveform indicates that the charge on capacitors 52-57 belonging to the - group of channels gradually increases to a predetermined value for each channel in that group selected for operation, at which point the capacitors are removed from the signal generator. The charge period (time) during which the charge is disconnected, τ, and the "hold" period (time), τ1, during which the charge remains or substantially remains at its charging voltage level for an additional time, during which the signal voltage is As shown in the figure, the signal voltage first rises above the charging voltage during this period, and returns to the charging voltage at the end of this period.After the period, the signal voltage becomes zero. This allows the signal generator to be recombined to the capacitor for the next operating phase.

Before that, rapid discharge of the capacitor takes place as described below.

During period τ1, the wall actuator electrodes of selected channels, e.g., odd-numbered channels 21 to 270, are energized to achieve the charging voltage and direction of polarization of the wall actuators as described in the co-pending European patent application. 5, causing outward deformation of the wall actuator in the form of a chevron or a protrusion from the flow path.

Since the voltage stop valve speed is slow, however, the amplitude of the sound wave formed in the ink flow path only slightly disturbs the ink meniscus in the flow path's injection nozzle, causing the actuated even numbered flow path to It is not enough to eject an ink drop from the nozzle of an adjacent even numbered channel.The charging period is the time when the sound wave travels through the active channel, and C is the acoustic wave velocity in the channel.

During the retention period τ, more ink is drawn into the odd-numbered channels actuated by the action of sound waves, and this causes the channel wall actuators to loosen outward as the amount of ink in the channels increases. . After a hold period, which is also typically L/C, the pressure of the ink in the selected channels is at its highest and the capacitors in those channels are then rapidly discharged to quickly move inside the channel actuator walls. movement, which generates pressure waves in selected channels that cause ink droplets to be ejected from the nozzles of those channels. After replenishing the channel in which the droplet ejection occurred, the next phase operation is performed in the selected even numbered channel according to the signal generator arrow (g phase).

The detailed operation of the drive circuit components of FIG. 2 will now be described.

In the quiescent state of the circuit, devices 143 to 147 and devices 153 to 157 are connected to the game)! Guided by an internally generated logic signal applied to the pole! (conducting) conditions while devices 123-127 are in non-conducting (non-conducting) conditions. Assuming that channel 25 is one of the group of odd numbered channels selected to be activated, at the beginning of the period τ□ of the signal from the signal generator initiated by the pulse on line 181, field effect device 125 is applied to its gate.
5 becomes conductive with a logic signal from device 14
The gate electrode signals at gate electrodes 5 and 155 are removed, rendering these devices non-conductive. So capacitors 54 and 55 are connected to a predetermined voltage during the period τ□ at field effect devices 125 and 154 in the case of capacitor 54 and at field effect devices 125 and 156 in the case of capacitor 55. The predetermined voltage is determined by the signal from the ROM stored in the register 175. The actuator wall of channel 25 is therefore moved outward to allow ink to flow into the sled channel;
Since the charging speed is slow, no ink droplets are ejected from the adjacent flow path.

During the hold period τ, the logic signal to the field effect device 125 is removed to disconnect the actuator from the drive circuit signals.

Firing, ie, discharging capacitors 54 and 55, connects the signal from resistor 175 to field effect devices 145 and 1 after a predetermined count of pulses on line 180.
55 to make bipolar transistor 135 conductive. This is applied to capacitor 54 via transistor 135 and diode 164, and transistor 13 for capacitor 55.
5 and a diode 166 to form a discharge path.

During discharge, when both field effect devices 145 and 155 are conductive, most of the discharge current flows through transistor 135 because bipolar transistor 135 and field effect device 155 are relatively resistive.

The discharge current of capacitors 54 and 55 is
35 and equally divided between diodes 164 and 166, and their relatively high discharge currents flow in clockwise and counterclockwise paths, respectively, thus effectively canceling their electromagnetic effects. Note that together they minimize radio frequency interference.

The heating effect of the current in circuit 101 is approximately limited to the capacitor discharge current, and thus the bipolar transistor turn-on time typically lasts 30 nanoseconds. Also, typically the discharge of capacitors 54 and 55 occurs in 2 P seconds, typically producing a current on the order of 100 mA, causing a rapid return of the actuator wall of flow path 25 to the relaxed position, causing the flow path Ink drop ejection pressure is generated at 25.

The discharge of similar ignition power capacitors 54 and 55 of all odd numbered channels activated in the same phase of operation occurs at the same time. In the next cycle of operation, the same waveform is applied to the wall electrodes of even numbered channels selected for activation.

FIG. 3 shows a portion of an alternative configuration of the two-phase multiplexer circuit of FIG. 2, which is a C-MO configuration. Parallel circuit 114.
115,116, the diodes are shunted with respective field effect transistors 194,195,196. The necessary logic signals to carry out the operation of this circuit are identical to those of the circuit of FIG. 2 and are not specifically shown.

At rest, devices 124-126 are in a non-conducting condition, and devices 194-196 are kept in a conducting state by a logic signal applied to their gate electrodes.

Assuming that in the first phase of operation of the circuit of FIG. Field effect device 125 from resistor 175 of 2
is charged by the logic signal applied to the gate electrode of device 195 and the removal of the signal at the gate electrode of device 195 . At the end of the period defined by the signal from the ROM stored in the combined register, the logic signal at the gate electrode of device 125 is removed and the charging of capacitors 54 and 55 is transferred to the same channel as channel 25. end at a level determined by the printed state of the channels on the opposite side of the channels 25 belonging to the group, and after a period of time a logic signal is applied to the gate electrode of device 175 to make the device conductive.
discharge. It is clear that this circuit has the same advantageous features as described in connection with the circuit of FIG.

A demand printhead for an inkjet section with drive circuits and connecting tracks formed and operated according to the principles described above offers the following advantages: 16 Each shear mode actuator wall participates in the operation of the channels on both sides of the alternating channel. do. Each channel is activated with both active walls at its boundaries. Each actuator wall is fired twice during each pre/trine operation of the drop. This configuration therefore provides effective use of piezoelectric actuators.

2. Even though the two actuators that operate each flow path have three drive tracks connected to operate them, the connecting track that connects the drive circuit to the actuators is the ink flow path! It has a density of llll tracks. Thus, for example, the channel 25 is connected to the drive circuit by track 75, but requires tracks 74, 75 and 76 to operate the actuator wall of the sled channel.

3. Large current (100
sJ) flows only in the local loop of the printhead.

Very little heat dissipated with this current is generated in the chip, ie only during the switching period of the discharge transistor.

4. There is no common ground circuit to collect the discharge current after the piezoelectric actuator discharges. Momentary (
In such a circuit, a very substantial current (64 or 128
It is necessary to configure the device to handle I00mA). Handling the magnitude of the current that is often applied during operation can lead to burnout accidents.

5. Electromagnetic effects from the discharge current are substantially canceled as the discharge current flows and returns in parallel closely spaced tracks of the dipole pair. This reduces the magnitude of the magnetic radiation quite significantly compared to what is expected to be generated in the common ground return loop.

6. Each channel of both the even and odd groups is operated with a voltage signal of the same polarity, which can be selected according to the polar direction of the ceramics in the piezoelectric actuator. A drive chip with a single polarity of the drive circuit consists only of p-type components and is cheaper in construction than a bipolar chip that requires both p- and n-type components.

7. The voltage signal operating each channel is compensated for the printing conditions of its opposite channel.

It will be clear to those skilled in the art that the switch devices of integrated circuits can have silicon controlled rectifiers, four-layer diodes or other types of semiconductor switch devices instead of field effect transistors and bipolar transistors.

Embodiments of the invention are illustrated in Figures 1.2 and 4 and Figures 1.3 and 4 in which the printhead flow paths are arranged in two groups of interleaved flow paths, with the flow paths of one group being staggered with the flow paths of the other group. However, it is clear to those skilled in the art that an array having three or more groups of channels can be used.

Thus, for example, in the case of three groups of interleaved channels, the circuit described would have two-phase operation, instead of the two-phase operation described for the circuits of FIGS. 2 and 3, for each group to be operated. channels are selected, and between two simultaneously activated channels there are fewer (both two inactive channels).For a given channel density, if the number of groups is large, then The higher the number, the more severe the crosstalk problem (but the longer it takes to print a print line, and the greater the spatial offset of each group of nozzles relative to the other groups of nozzles). The necessity complicates the printhead construction; preferably the highest achievable flowpath densities require adjacent wall deflections to limit crosstalk by grouping the flowpaths and compensating the charging voltage of the flowpath capacitors. This may be due to the printing condition of the flow path.

[Brief explanation of drawings]

Figure 1 shows co-pending European patent application 488300146
．． 3 shows a cross-section of an inkjet printhead with a shear mode wall actuator as described in FIG. FIG. 2 shows one embodiment of a multiplexer circuit connected to the shear mode actuator of the printhead shown in FIG. FIG. 3 shows a second embodiment of a multiplexer circuit for use with the shear mode actuator of FIG. FIG. 4 shows suitable waveforms for operating the inkjet printhead of FIG. 1 using the circuit of FIG. 2 or 3. Engraving of the drawings (no changes to the contents) Fla. 1. Applicant: AM International Incorporated Agent Patent attorney: Takeshi Saito 2. Agent

Claims (1)

Claims: 1. A multiplexer circuit for operating selected devices of each group of devices in a series of capacitively actuated devices in successive operating phases, the circuit connecting the respective devices; The circuit has a series of parallel connected circuits arranged in parallel with the signal generator, and the circuits are connected in parallel with the signal generator, and the circuits of the combined device and the circuit of the combined device are connected in parallel. two capacitors of each device connected between respective electrical circuits on the opposite side; first and second capacitors disposed in each electrical circuit and configured to be closed by respective logic signals applied thereto; a switching member, the first and second switching members of one electric path are closed and opened, respectively, and the first and second switching members of each electric path on opposite sides of the one electric path are respectively closed and opened.
When the switching members are respectively opened and closed,
Charging of a capacitor connected to the one electrical circuit occurs, and then discharging of the capacitor connected to the one electrical circuit occurs when the first and second switching members of the one electrical circuit are opened and closed, respectively. A multiplexer circuit featuring: 2. The multiplexer circuit of claim 1, wherein said devices of said series of devices are arranged as two groups of interleaved devices. 3. The multiplexer circuit of claim 2, wherein the devices of the first group of the group are staggered in the series with respect to each device of the second group of the group. 4. A diode device is connected across the second switching member of each circuit, and a conductive path for discharging a capacitor is connected between the circuit to which the diode is connected and the circuit on the opposite side of each. 4. A multiplexer circuit according to claim 1, wherein the multiplexer circuit provides a multiplexer circuit according to claim 1. 5. The multiplexer circuit according to claim 1, wherein the first and second switching members are provided on a silicon chip integrated circuit, and the switching members are transistor switches. 6. The multiplexer circuit of claim 5, wherein the transistor switch comprises a field effect transistor. 7. the second switching member of each electrical path has first and second switching components; the first switching component is connected between the electrical path containing the second switching member and the opposing electrical path; providing a bypass circuit parallel to a second switching component utilizing a first switching member of the circuit opposite the circuit including the second switching member when charging the capacitor; 4. After charging a capacitor connected to an electrical path, a second switching component provides a discharge path for the capacitor utilizing a first switching member included in the same electrical path as the second switching component. 7. The multiplexer circuit according to any one of 1 to 6. 8. first and second switching members are provided on a silicon chip integrated circuit, the first switching member comprising a field effect transistor, and the first and second switching components of the second switching member comprising a field effect transistor and a field effect transistor, respectively; 8. The multiplexer circuit of claim 7 comprising bipolar transistors with field effect transistor conduction control. 9. The capacitors connected to the devices selected for operation in each phase of operation are charged with the initial part of the voltage waveform supplied by the signal generator, and then the capacitors connected to the devices selected for operation are 9. A multiplexer circuit according to claim 1, characterized in that the signal generator is decoupled from the circuit for further periods of the waveform. 10. A multiplexer circuit according to claim 1, wherein the signal generator, the parallel circuit and the first and second switching members thereof are provided on a silicon chip integrated circuit. 11. The multiplexer circuit according to claim 1, wherein the logic signal applying member is provided for switching on and off the first and second switching members. 12. A logic signal applying member applies a signal to the first and second switching members to cause the capacitor of each device selected for activation to be activated or to activate a device adjacent to each of the selected devices. 12. The multiplexer circuit according to claim 11, wherein the multiplexer circuit is configured to be able to be charged for a period of time depending on the non-operating state. 13. Multi-channel arrangement for attaching droplets to the surface;
An electrically pulsed drop deposition device, the device comprising: a drop deposition head formed from an electrically active material; multiple channels arranged in multiple groups for liquid formed in the head; nozzles communicating with the flow channels, longitudinal side walls each serving to separate one flow channel from the next, and for causing lateral displacement of the longitudinal side walls of each flow channel in opposite directions; an electrically actuating member, the electrically actuating member comprising an electrode on each opposing surface in each channel of the longitudinal channel sidewall, a conductive member connecting the electrodes of each channel; so that the electrodes and the channel sidewalls form a series capacitor, each consisting of a capacitor of one of the longitudinal channel sidewalls and an electrode on the opposite side thereof, and a multiplexer circuit for effecting the actuation of the longitudinal channel walls of the flow channel in successive operating phases; conduction between a signal generator connected to both ends of the parallel electric circuits, first and second switching members disposed on each of the electric circuits, and the first and second switching members, which are connected to each other and connected to both ends of the parallel electric circuits; the first and second switching members of one electric path are closed and opened, respectively, and the first and second switching members of each electric path on opposite sides of the one electric path; Charging of the capacitor connected to the one circuit occurs when the first and second circuits of the one circuit are opened and closed, respectively.
An electric pulse type drop deposition device characterized in that discharge of the capacitor occurs when the switching member is closed and opened, respectively. 14. The pulsed droplet deposition apparatus of claim 13, wherein the channels are arranged in groups of a plurality of interleaved channels. 15. The channels are divided into two groups, and the first of the two groups
15. The pulsed droplet deposition device according to claim 14, wherein the flow channels of the groups are arranged alternately with the flow channels of each of the second groups. 16. The signal generator supplies a relatively slowly increasing voltage signal to the capacitor in the selected flow path when charging the capacitor, and when the logic signal application member reaches a predetermined charging voltage; The signal generator is disconnected from the capacitor in the selected flow path and the switching member is activated at intervals to rapidly discharge the charged capacitor, Pulsed drop deposition according to any one of claims 13 to 15, characterized in that the longitudinal side walls of the channel are displaced relatively gradually outwards and the channel walls return rapidly upon discharge of the capacitor. Device. 17. Applying a signal to the first and second switching members of each of the parallel circuits to which the logic signal applying member connects the capacitor of the selected channel, Claim characterized in that the arrangement is such that the capacitor is charged for a certain period of time to provide a voltage level of the capacitor that depends on the selected or unselected state of the group containing the selected channel and the channels adjacent to the selected channel. The pulse type droplet deposition device according to any one of Items 13 to 16.