JPH0218734B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention particularly relates to an abnormality detection device for a microcomputer.

<Prior Art> In recent years, microcomputers (hereinafter referred to as microcomputers) have been widely used as various control devices. In this case, if an abnormality occurs in the microcomputer, the microcomputer will run out of control and will not be able to perform normal control.
As a safety measure, a device is usually provided to detect abnormalities in the microcomputer.

Such a conventional abnormality detection device extracts an abnormality detection signal based on a data signal of a data bus of a microcomputer, and the microcontroller itself reads the abnormality detection signal to determine whether or not an abnormality exists, and performs abnormality detection. ing.

<Problems to be Solved by the Invention> However, with this type of abnormality detection performed by the microcomputer itself, the abnormality detection function itself may become abnormal when an abnormality occurs in the microcomputer, so accurate detection cannot be performed, and the microcomputer There was a problem in terms of reliability as it was not always possible to reliably prevent runaway behavior.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an abnormality detection device that can accurately detect abnormalities in a microcomputer and reliably prevent runaway.

<Means for Solving the Problems> Therefore, the present invention provides a signal forming circuit that forms an abnormality determination signal based on a data signal of a microcomputer, and a signal forming circuit that inputs a signal from the signal forming circuit to generate the data signal. It is composed of an abnormality determination circuit that determines whether or not there is an abnormality, stores this information in the event of an abnormality, and outputs an abnormality determination signal even when its own abnormality occurs.

<Function> As a result, when a microcomputer abnormality occurs, the abnormality determination circuit detects this and outputs it to a circuit that stops power supply to the microcomputer, for example, to put the microcomputer in an inoperable state and reliably prevent the microcomputer from running out of control. Also,
When a failure occurs inside the abnormality determination circuit, the failure is detected by the abnormality determination circuit itself, and the operation of the microcomputer is stopped in the same manner as described above.

<Example> An example of the present invention will be described below based on the drawings.

FIG. 1 is a circuit diagram of the main part of this embodiment, and FIG. 2 is a block diagram showing the configuration of this embodiment.

First, the schematic configuration of this embodiment will be explained based on FIG. 2.

In the figure, 1 and 2 are microcomputers each having, for example, 8-bit data buses _{a 0 to a 7} and b _{0 to} b _{7 .} b ₇ are configured to output the same data signal. 10 is a signal forming circuit that inputs data signals from the data buses _a0 to _a7 , _b0 to _b7 of each of the microcomputers 1 and 2 and forms an abnormality detection signal; Outputs a pair of abnormality detection signals from 16 data signals. Reference numeral 20 denotes an abnormality determination circuit that determines whether or not the microcomputers 1 and 2 are abnormal based on the pair of abnormality detection signals from the signal forming circuit 10, and when abnormal, stores this information and outputs an abnormality determination signal. . Further, the abnormality determination circuit 20 outputs an abnormality determination signal even when its own abnormality occurs. Reference numeral 30 denotes a drive circuit that opens a relay 3 interposed in the energizing circuit to each microcomputer 1, 2 when the abnormality determination signal is output. It consists of Note that 4 is a power supply, and 5 is a power switch for the microcomputers 1 and 2.

Next, the configurations of the signal forming circuit and the abnormality determining circuit will be described in detail based on FIG.

First, the signal forming circuit 10 consists of seven comparison circuits 11 to 17 having the same configuration. The configuration of the comparison circuits 11 to 17 will be explained by taking the comparison circuit 11 as an example. Four AND circuits A ₁ to _{A 4}
and two OR circuits B ₁ , B ₂ and two inverters
D ₁ and D ₂ , and AND circuits A ₁ to _{A 4} receive data signals from data buses a ₀ and a ₁ of microcomputer 1 and inverted signals of data signals from data buses b ₀ and b ₁ of microcomputer 2. There are two inputs each in a predetermined combination, the outputs of AND circuits A ₁ and A ₂ are input to OR circuit B ₁ , and the outputs of AND circuits A ₃ and A ₄ are input to OR circuit B ₂ . Furthermore, the data signal of the microcomputer 2 is inverted by inverters _D1 and _D2 , respectively, and then converted into a predetermined AND signal.
input to the circuit. The outputs of the comparison circuits 11 and 12 are sent to the next stage comparison circuit 15, and the outputs of the comparison circuits 11 and 12
The outputs of the comparators 3 and 14 are input to the comparator circuit 16, and the outputs of the comparator circuits 15 and 16 are input to the comparator circuit 1.
7, and ultimately generates two pairs of abnormality detection signals from the 16 data signals from the microcomputers 1 and 2.

Next, the configuration of the abnormality determination circuit will be explained.

The abnormality determination circuit 20 of this embodiment includes a first delay circuit 21 that delays one of the pair of determination detection signals outputted from the signal forming circuit 10, and a first delay circuit 21 that delays one of the pair of determination detection signals outputted from the signal forming circuit 10, and a first delay circuit 21 that delays one of the pair of determination detection signals outputted from the signal forming circuit 10, and a first delay circuit 21 that delays one of the pair of determination detection signals outputted from the signal forming circuit 10, and a first delay circuit 21 that delays one of the pair of determination detection signals output from the signal forming circuit 10. A first Exclusive input signal is inputted through the circuit 21 and outputted when both input signals have opposite output levels.
The OR circuit (hereinafter referred to as the first EOR circuit) 22 and the
a first flip-flop circuit (hereinafter referred to as the first F.F circuit) 23 that stores and holds an input signal using the output of the 1EOR circuit 22 as a trigger signal and outputs it;
A second delay circuit 24 that delays one of the outputs of the first F.F circuit 23 that is input to a second Exclusive OR circuit (hereinafter referred to as a second EOR circuit) 25, which will be described later;
The output of the 1F/F circuit 23 is inputted directly and via the second delay circuit 24, respectively, and output when both input signals are at opposite output levels.
2EOR circuit 25 and a second flip-flop circuit (hereinafter referred to as 2nd F.F.
circuit) 26, and the second F/F circuit 26
The output is input to the 1st F・F circuit 23, and the abnormality detection signal input directly to the 1st EOR circuit 22 is input to the 2nd F・F circuit 23.
The signal is input to the F circuit 26, and both outputs of the first and second F/F circuits 23, 26 are outputted to the drive circuit 30 as an abnormality determination signal.

In the initial state, the first F.F circuit 23 is set by the input of the set signal S and its output becomes "1", and the second F.F circuit 26 is set by the input of the reset signal R.
It is reset by the input of , so that the output becomes "0".

Next, the operation will be explained with reference to the time charts of FIGS. 3 and 4.

First, the operation of the signal forming circuit 10 when the microcomputers 1 and 2 are normal will be described. Microcomputer 1,
2 is normal, the microcomputers 1 and 2 are synchronized, and the same data signals are output from the data buses a ₀ and b ₀ , . . . a ₇ and b ₇ .

For example, if a ₀ = b ₀ = “1” and a data signal of a ₁ = b ₁ = “0” is output, the comparison circuit 11
The outputs of AND circuits A ₁ to _{A 4} are “1”, “0”, and
It becomes “0”, “0”. Therefore, the output of OR circuit _B1 becomes "1" and the output of OR circuit _B2 becomes "0". In this way, under normal conditions, the two outputs of the comparator circuit 11 are inverted from each other. This is the same for each comparison circuit 12 to 17. Therefore, when the microcomputers 1 and 2 are normal, the 2 output from the final comparison circuit 17 of the signal forming circuit 10 is
The two abnormality detection signals are output as "1" and "0" signals that are inverted from each other.

Next, the operation of the abnormality determination circuit 20 will be explained with reference to the time chart shown in FIG.

Now, the two outputs of the signal forming circuit 10 are
Let them be C ₁ and C ₂ . Then, when contradictory pulse signals are output from C ₁ and C ₂ as shown in FIG. 3, C ₁ ,
The outputs of C ₂ are both input to the first EOR circuit 22,
C ₁ is input directly, C ₂ is input to the first delay circuit 2
1, and is inputted after being delayed by _t1 time as shown in the third figure (see C3 in FIG. ₃ ). Therefore, the first EOR circuit 2
The output of 2 is as shown in C ₄ in Figure 3. This first
The output of the 1EOR circuit 22 is input to the first F/F circuit 23, and the first F/F circuit 23 is triggered when the output of the first EOR circuit 22 is "1", and the output of the second F/F circuit 26 is input at that time. It stores and outputs this. In the initial state, the first F.F circuit 23 outputs "1" due to the set signal S, and the output _C8 of the second F.F circuit 26 becomes "0" due to the reset signal R. So, the first
The 1F/F circuit 23 stores and holds "0" in response to the first trigger signal of the first EOR circuit 22, and its output changes from "1" to "0" (see _C5 in FIG. 3).

Next, the output _C5 of the first F.F circuit 23 is input to the second EOR circuit 25 directly and after being delayed for _t2 time via the second delay circuit 24 (see _C6 in FIG. 3). Therefore, the output C ₇ of the second EOR circuit 25 becomes as shown in the third diagram, and rises to trigger the second F·F circuit 26 when the output C ₅ of the first F·F circuit 23 changes. Then, the second F/F circuit 26 stores and outputs " ₁ " of one output C1 of the input signal forming circuit 10 according to the trigger signal, so that its output _C8 becomes "0". ” to “1”.

Through the above operations, the signal forming circuit 10
When the outputs C ₁ and C ₂ of the circuit normally output pulse signals inverted from each other, the output time chart from each circuit of the abnormality determination circuit 20 becomes as shown in FIG. The outputs, ie, the outputs C ₅ and C ₈ of the first and second F·F circuits 23 and 26, are pulse signals having the same phase and are inverted from each other.

Next, a case where an abnormality occurs in the microcomputer 1 or 2 will be explained.

For example, an error occurs in microcomputer 2 and the data bus b ₀ ~
Suppose that one of _b7 , for example _b0 , has a data signal of "1" and outputs "0". Then, a ₀ = “1”, b ₀
= “0” and a ₁ = b ₁ = “0”, then 4 AND
The outputs of circuits A ₁ to _{A 4} are “1”, “0”, “0”, “1”
Therefore, the outputs of OR circuits B ₁ and B ₂ both become "1". In this way, when an abnormality occurs in microcomputer 1 or 2, 2 of the comparator circuit to which the abnormal data signal is input
Therefore, the outputs C ₁ and C ₂ of the signal forming circuit 10 become the same.

Now, suppose that an abnormal signal is generated at the output _C2 only once as shown in FIG. 4, and the output _C2 does not fall and continues to output a signal of "1". Then, normally, the trigger signal would be output from the first EOR circuit 22 at the falling signal of the output C ₃ from the first delay circuit 21, but in this case, the trigger signal is output from the output C ₁
At the falling signal of , the output _C4 of the first EOR circuit 22 becomes "1" and a trigger signal is output to the first F.F circuit 23. At this time, the 1st F/F circuit 2
3 stores and outputs "0" of the output _C8 of the second F.F circuit 26. And the second EOR circuit 2
5, when the output C ₅ of the first F.F circuit 23 changes from "1" to "0", its output C ₇ becomes "1" and triggers the second F.F circuit 26. At this point, the output C ₁ is "1", so the second F.F circuit 26 stores "1" and its output C ₈
changes from “0” to “1”.

Then, if the microcomputer 2 returns to normal again and the output C ₂ returns to normal, the output C ₄ of the first EOR circuit ₂₂ becomes “ 1”
The 1F/F circuit 23 is triggered, stores and holds the input "1" at that time, and output _C5 changes from "0" to "1". synchronized with the change in this output _C5 .
The 2F/F circuit 26 is triggered and the output _C1 becomes “1”
is stored and output, but the 2nd F and F
The output _C8 of the circuit 26 is “1”, and the
The output _C8 of the 2F/F circuit 26 does not change and remains at "1".

Therefore, even if the first F.F circuit 23 is triggered next time, its output _C5 remains at "1" and does not change.

Due to this operation, at least when the microcomputer 1 or 2 is abnormal, the outputs C ₅ and C ₈ of the abnormality determination circuit 20 do not become pulse signals, but become DC signals of the same level.

By the way, according to the abnormality determination circuit 20 of this embodiment, an abnormality determination signal is output even when a failure occurs in the abnormality determination circuit 20 itself.

The following describes the operation when such a failure occurs.

For example, if the first delay circuit 21 fails and the delay function no longer operates, the first EOR circuit 21
The output _C4 does not change after rising from "0" to "1" once. For this reason, the 1st F.
Circuit 23 only needs to be triggered once and then outputs
There is no change in _C5 , and as a result, the second EOR circuit 25 only rises from “0” to “1” once, and the
Since the 2F/F circuit 26 is also triggered only once, the outputs C ₅ and C ₈ of the abnormality determination circuit 20 do not change and are no longer AC waveforms, similar to when the microcomputer is abnormal.

In addition, when the second delay circuit 24 fails, the second EOR
The output C ₇ of the circuit 25 does not rise and the second F.F circuit 26 is not triggered. For this reason, the 1st F.
Although the circuit 23 is normally triggered, its output does not change, so the output of the abnormality determination circuit 20 does not change.
C ₅ and C ₈ are no longer AC waveforms.

Next, if the first EOR circuit 22 or the second EOR circuit 25 fails, the first and second F/F circuits 23,
26 is no longer triggered, the outputs C ₅ and C ₈ of the abnormality determination circuit 20 no longer have AC waveforms.
Furthermore, when the output side of the first or second F/F circuit 23 or 26 fails and the output no longer changes, needless to say, the outputs C ₅ and C ₈ of the abnormality determination circuit 20 no longer have AC waveforms.

Furthermore, due to a failure of the first and second F/F circuits 23 and 26, the input signal may be outputted as an output signal.

First, when the failure occurs in the first F.F circuit 23, the output _C5 of the first F.F circuit 23 changes in synchronization with the change in the output _C8 of the second F.F circuit 26,
And the output will be at the same level. Therefore, the same pulse signal is outputted from the abnormality determination circuit 20. Further, if a failure occurs in the second F.F circuit 26, the second F.F circuit 26 is connected to the signal forming circuit 10.
Its output C ₈ changes in synchronization with the change in output C ₁ of
On the other hand, the output C ₅ of the first F·F circuit 23 is delayed by the delay time t ₁ of the first delay circuit 21 and changes.
The abnormality determination circuit 20 outputs pulse signals whose phases are shifted from each other for an hour _t1 . Furthermore, if both the microcomputer and the second F/F circuits 23 and 26 fail, their outputs C ₅ and C ₈ will change in synchronization with the change in the output C ₁ of the signal forming circuit 10.
The output of the abnormality determination circuit 20 becomes the same pulse signal.

Then, an output signal based on the operation of the abnormality determination circuit 20 described above is output to the drive circuit 30. This drive circuit 30 is constituted by an AC amplification circuit that performs an amplification effect only when pulse signals of the same phase and mutually inverted are outputted during normal operation as described above. Therefore, only in normal conditions, relay 3 is energized and its contacts are kept closed, allowing power to be applied to microcontrollers 1 and 2. In abnormal conditions, relay 3 is demagnetized and its contacts are opened, so microcontroller 1 , 2 is cut off, rendering the microcomputers 1 and 2 inoperable.
In addition, in the initial state, the first and second F/F circuits 23, which are output in synchronization with the ON operation of the power switch 5,
Based on the outputs of the second F and F circuits 23 and 26 by the set signal S and reset signal R to 26, the relay 3 is excited, the contacts are closed, and the microcontrollers 1 and 2 are energized, and if normal. Continued.

Therefore, the microcomputers 1 and 2 and the abnormality determination circuit 20
In the event of an abnormality, this information can be stored and the operation of the microcomputers 1 and 2 can be reliably maintained in a stopped state, thereby preventing the microcomputers 1 and 2 from running out of control.

Although this embodiment shows an example of abnormality detection in a microcomputer, it goes without saying that the invention is not limited to this and can be applied to abnormality detection in other control devices that output mutually contradictory pulse signals. Further, the configuration for stopping the operation of the microcomputer in the event of an abnormality is not limited to this embodiment, and any configuration that stops the power supply to the microcomputer may be used.

<Effects of the Invention> As described above, according to the present invention, when an abnormality occurs in the microcomputer, the abnormality is detected and stored, and, for example, the power supply to the microcomputer is stopped.
In the event of an abnormality, the operation of the microcomputer is reliably stopped and the status is memorized, making it possible to more reliably prevent the microcomputer from running out of control. Furthermore, since the operation of the microcomputer is stopped even when the abnormality determination circuit itself fails, safety is significantly improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of the main part of one embodiment of the present invention, and FIG.
The figure is an overall block diagram of the above embodiment, and Figures 3 and 4 are time charts for explaining the operation of the above embodiment. Figure 3 shows an example in normal operation, and Figure 4 shows an example in the event of abnormality. It is something. 1, 2...Microcomputer, 3...Relay, 4...Power supply, 1
0... Signal forming circuit, 20... Abnormality determination circuit, 21...
1st delay circuit, 22...1st EOR circuit, 23...th
1F/F circuit, 24...second delay circuit, 25...second
2EOR circuit, 26...2nd F/F circuit, 30...drive circuit.

Claims (1)

[Scope of Claims] 1. An abnormality detection device that detects an abnormality in a microcomputer based on a data signal of the microcomputer, comprising a signal forming circuit that forms an abnormality detection signal based on the data signal, and a signal forming circuit that forms an abnormality detection signal based on the data signal. a data signal determination circuit that determines whether or not the data signal is abnormal based on a signal from the circuit; a memory circuit that stores and retains the abnormality determination in the event of an abnormality; and a self-operation determination circuit that performs the abnormality determination and the abnormality determination of the memory retention operation. What is claimed is: 1. An abnormality detection device for a microcomputer, characterized in that it is configured to include an abnormality determination circuit consisting of a circuit. 2. The abnormality determination circuit receives one of the pair of abnormality detection signals from the signal forming circuit directly, inputs the other through the first delay circuit, and outputs the first signal when both input signals have opposite output levels. a logic circuit, a first memory circuit that stores and outputs an input signal using the output of the first logic circuit as a trigger signal, and inputs the output of the first memory circuit directly and through a second delay circuit, respectively. and a second logic circuit that outputs an output when both input signals have opposite output levels, and a second storage circuit that stores and outputs the input signal using the output of the second logic circuit as a trigger signal. The output of the two memory circuits is input to the first memory circuit, and the abnormality detection signal of one of the signal forming circuits directly input to the first logic circuit is input to the second memory circuit. An abnormality detection device for a microcomputer according to claim 1, wherein both outputs are configured to output as an abnormality determination signal.