JPH0218779B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an improvement in a test method for a synchronization signal reception protection circuit built into a synchronization signal reception circuit.

(b) Technical Background Figure 1 is a diagram showing an example of a synchronous signal receiving circuit used in digital exchanges, etc.
The figure is a diagram showing an example of various signal waveforms in FIG. 1. In FIGS. 1 and 2, a synchronization signal receiving circuit 1 monitors the normality of a received frame synchronization signal fs, and outputs an abnormality signal a1 if the frame synchronization signal fs is not received normally. Note that the synchronization signal receiving circuit 1 has a built-in synchronization signal reception protection circuit, and if an allowable pulse dropout occurs in the frame synchronization signal fs, it does not send out the abnormal signal a1 (backward protection function). Even if the reception of the frame synchronization signal fs that has been in a stopped state starts, it is determined that reception has started normally only after a predetermined number of pulses are continuously received, and the output of the abnormal signal a1 is stopped (forward protection function). . The synchronization signal reception protection circuit is 1
If the backward protection function of the stage is provided, even if one pulse of the frame synchronization signal fs is missing at time t1 as shown in FIG.
is not output, and the abnormal signal a1 is output only when two pulses are consecutively missed at times t2 and t3. Furthermore, if the synchronization signal reception protection circuit has a three-stage forward protection function, even if the frame synchronization signal fs, which had been stopped until time t5, starts receiving from time t6, the output of the abnormal signal a1 will not stop immediately. , the output of the abnormal signal a1 is stopped only when four pulses are continuously received by time t9.

(c) Prior Art and Problems Conventionally, in order to test the backward and forward protection functions of the synchronization signal reception protection circuit built into this type of synchronization signal reception circuit, the frame input to the synchronization signal reception circuit 1 to be tested is The backward protection function is tested by stopping the synchronization signal fs at the reference time and measuring the elapsed time until the abnormal signal a1 is output, and by starting inputting the stopped frame synchronization signal fs at the reference time and testing. The forward protection function was tested by measuring the elapsed time until the abnormal signal a1 being outputted from the target synchronization signal receiving circuit 1 stopped. Measuring such a transient phenomenon time is not necessarily easy, requires a lot of effort, is prone to errors, and has the disadvantage that reliable testing cannot be performed.

(d) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional testing methods for synchronous signal reception protection circuits as described above, and to realize means that can easily and reliably test the synchronous signal reception protection circuits. There is a particular thing.

(e) Structure of the Invention The object of the present invention is to provide a shift register that steps cyclically in synchronization with a predetermined synchronization signal, a means for setting arbitrary initial data in the shift register, and a method for outputting data from the highest digit of the shift register. and a gate whose conduction state is controlled by the logic value of the bit to be tested, and each pulse of the continuous synchronization signal passing through the gate is arbitrarily transmitted or stopped and inputted to the synchronization signal receiving circuit under test. This can be achieved by testing the synchronization signal reception protection circuit built into the synchronization signal reception circuit.

(f) Embodiment of the invention Hereinafter, an embodiment of the invention will be described with reference to the drawings.
FIG. 3 is a diagram showing a test method for a synchronization signal reception protection circuit according to an embodiment of the present invention, and FIG.
FIG. 5 is a diagram showing an example of the various signal waveforms in FIG. 4, and FIG. 6 is a diagram showing an example of the test procedure for the rear protection function in FIG. 3. FIG. 7 is a diagram showing an example of a test procedure for the forward protection function in FIG. 3. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 3, the test apparatus 2 includes a control circuit 3 that controls the overall test procedure for the synchronous signal receiving circuit 1 to be tested, a control register 4 that supplies various frame synchronous signals fs for testing to the synchronous signal receiving circuit 1, and a synchronous It is comprised of a signal control circuit 5, a synchronization signal generation circuit 6, and an interface circuit 7 that receives the abnormal signal a1 output from the synchronization signal reception circuit 1. The method of outputting the frame synchronization signal fs in the control register 4, synchronization signal control circuit 5, and synchronization signal generation circuit 6 is composed of a shift register 8 and a gate 9, as shown in FIG. The shift register 8 consists of 24 bits, and increments the initial data ID set from the outside by one bit in the upper direction in synchronization with the continuous synchronization signal cs, and the output bit ob output from the most significant bit MSB is again It is cyclically input to the least significant bit LSB and is also transmitted to the negative input terminal of gate 9. As a result, gate 9 outputs a logical 0 bit.
When ob is transmitted, it becomes conductive, and when the output bit ob of logic value 1 is transmitted, it becomes blocked. A continuous synchronizing signal cs is input to the other input terminal of the gate 9. The initial data ID set in shift register 8 has a logical value of 0 for all 24 bits.
(Hereafter, it will be displayed in hexadecimal as 000000), then
The output bit ob, which always has a logic value of 0, is output from the shift register 8, the gate 9 is always in a conductive state, and the continuous synchronization signal cs becomes the frame synchronization signal fs.
is output as Next, when initial data id = 000001 is set, the shift register 8 outputs the output bit ob of logical value 0 23 times in a row, and then
The state of outputting the output bit ob of logical value 1 is repeated [ob (000001) in Fig. 5]. Therefore, the gate 9 enters the blocking state only when the output bit ob of logical value 1 is transmitted, and stops sending out one pulse of the continuous synchronizing signal cs. As a result, the gate 9 outputs a frame synchronization signal fs (000001) that repeatedly transmits 23 pulses continuously and stops transmitting one pulse. Similarly initial data
If you set id=000003, the output bit ob(000003)
is a logical value 0 for 22 consecutive times and a logical value 1 for 2 consecutive times
The frame synchronization signal fs (000003) is repeated alternately.
alternately repeats continuous sending of 22 pulses and stopping continuous sending of 2 pulses. Further, if the initial data id=AAAAAA is set, the output bit ob (AAAAAA) alternately repeats a logic value of 0 and a logic value of 1, and the frame synchronization signal fs (AAAAAA) repeats sending and stopping of sending for each pulse. Furthermore, if the initial data id = 924924 is set, the output bit ob (924924) will alternately repeat the logical value 1 once and the logical value 0 twice in succession,
The frame synchronization signal fs (924924) alternately repeats continuous transmission of two pulses and stop of transmission of one pulse. If the synchronous signal receiving circuit 1 under test connected to the test device 2 has a built-in synchronous signal receiving protection circuit having a 1-stage backward protection function and a 1-stage forward protection function, the control circuit 3 in FIG. After setting the initial data ID = 000001 to the shift register 8 in the synchronization signal control circuit 5 via the control register 4, the synchronization signal receiving circuit 1 is operated for 2 milliseconds (steps S1 and S2), and if it operates normally, the test is completed. (steps S3 and S4). A frame synchronization signal fs is sent from the synchronization signal generation circuit 6 to the synchronization signal reception circuit 1.
(000001) is supplied for 2 milliseconds, if the abnormal signal a1 is not returned from the synchronization signal receiving circuit 1 to the interface circuit 7 (steps S5 to S7), the control circuit 3 temporarily stops the test (step S8). ), set initial data id = 000003 (step S9 and
S10) Repeat the procedure after step S2 again. If the abnormal signal a1 is returned from the synchronization signal reception circuit 1 while the frame synchronization signal fs (000003) is supplied from the synchronization signal generation circuit 6 to the synchronization signal reception circuit 1 for 2 milliseconds (steps S5, S6, and S11). , the one-stage backward protection function of the synchronization signal reception protection circuit built in the synchronization signal reception circuit 1 under test is determined to be normal, and the test is completed (steps S8 and S9). If the initial data ID is 000001 and the abnormal signal a1 is returned from the synchronization signal receiving circuit 1 (steps S5 and S6
and S11), or if the abnormal signal a1 is not returned from the synchronization signal reception circuit 1 when the initial data ID is 000003 (steps S5 to S7), the synchronization signal reception protection built in the synchronization signal reception circuit 1 under test The one-stage backward protection function of the circuit determines that there is an abnormality and outputs an appropriate display. Next, in FIG. 7, the control circuit 3 connects the synchronizing signal control circuit 5 to
Initial data id = in shift register 8 in
After setting AAAAAA, the synchronizing signal receiving circuit 1 is operated for 2 milliseconds (steps S21 and S22), and when the abnormal signal a1 is returned to the interface circuit 7, the test is started (steps S23 and S24). While the frame synchronization signal fs (AAAAAA) is supplied from the synchronization signal generation circuit 6 to the synchronization signal reception circuit 1 for 2 milliseconds, the abnormal signal a from the synchronization signal reception circuit 1
1 does not stop (steps S25 to S27), the control circuit 3 temporarily stops the test (step S28), sets initial data ID=924924 (steps 29 and S30), and repeats the procedure after step S22 again.
While the frame synchronization signal fs (924924) is supplied from the synchronization signal generation circuit 6 to the synchronization signal reception circuit 1 for 2 milliseconds, the abnormal signal a1 from the synchronization signal reception circuit 1
stops (steps S25, S26, and S31), it is determined that the first stage forward protection function of the synchronization signal reception protection circuit built in the synchronization signal reception circuit 1 under test is normal.
Test completed (steps S28 and S29). If the initial data ID is AAAAAA and the abnormal signal a1 from the synchronization signal receiving circuit 1 stops (steps S25, S26 and S31), or if the initial data ID is
924924, if the abnormal signal a1 from the synchronization signal receiving circuit 1 does not stop (step S25,
S26 and S27), the one-stage forward protection function of the synchronization signal reception protection circuit built in the synchronization signal reception circuit 1 under test is determined to be abnormal, and an appropriate display is output.

As is clear from the above description, according to this embodiment, the test device 2 sequentially sends the frame synchronization signal fs that matches the number of rear and front protection stages of the synchronization signal reception protection circuit built in the synchronization signal reception circuit 1 under test. The backward protection function and forward protection function of the synchronization signal reception protection circuit can be automatically and reliably tested.

Note that FIGS. 3 to 7 are only one embodiment of the present invention, and for example, the numbers of rear and front protection stages of the synchronization signal reception protection circuit built in the synchronization signal reception circuit 1 under test are as shown in the figures. Although there are no limitations and many other modifications may be considered, the effects of the present invention remain the same in either case. Furthermore, the configuration of the test device 2 is not limited to that shown in the drawings, and many other modifications may be considered, but the effects of the present invention remain the same in any case. Furthermore, it goes without saying that the synchronization signal targeted by the present invention is not limited to a frame synchronization signal.

(g) Effects of the Invention As described above, according to the present invention, it is possible to automatically and reliably test the backward and forward protection functions provided in the synchronization signal reception protection circuit, and the test man-hours are reduced and the test accuracy is significantly improved. I can figure it out.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a synchronization signal reception circuit, FIG. 2 is a diagram showing an example of various signal waveforms in FIG. 1, and FIG. 3 is a test method for a synchronization signal reception protection circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing the output method of the frame synchronization signal in FIG.
Fig. 5 is a diagram showing an example of various signal waveforms in Fig. 4, Fig. 6 is a diagram showing an example of the test procedure for the rear protection function in Fig. 3, and Fig. 7 is a diagram showing an example of the test procedure for the forward protection function in Fig. 3. It is a figure which shows an example of a procedure. In the figure, 1 is a synchronization signal receiving circuit, 2 is a test device, 3 is a control circuit, 4 is a control register, 5 is a synchronization signal control circuit, 6 is a synchronization signal generation circuit, 7 is an interface circuit, 8 is a shift register, 9 is a gate, a1 is an abnormal signal, cs is a continuous synchronization signal, fs is a frame synchronization signal, id is initial data, ob is an output bit, and t1 to t9 are time points.

Claims (1)

[Claims] 1 A shift register that advances cyclically in synchronization with a predetermined synchronization signal, means for setting arbitrary initial data in the shift register, and a conduction state based on the logical value of the bit output from the highest digit of the shift register. By providing a gate controlled by the synchronous signal receiving circuit under test, each pulse of the continuous synchronous signal passing through the gate is arbitrarily transmitted or stopped and inputted to the synchronous signal receiving circuit under test. A test method for a synchronous signal reception protection circuit characterized by testing a built-in synchronous signal reception protection circuit.