JPH02187880A - One chip microcomputer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to the configuration of a one-chip microcomputer that is used semi-customly for various purposes.

[Prior Art] The configuration of conventional one-chip microcomputers differs depending on the purpose for which the microcomputer is used.

[Problem to be solved by the invention] Therefore, with conventional technology, it takes a lot of time to develop a one-chip micro combinator that is suitable for a certain purpose, and if the configuration of instructions etc. is different, The problem is that the assets of the developed program cannot be effectively utilized.

The present invention is intended to solve these problems, and its purpose is to shorten the development period for all uses by creating a core CPU that can have the same configuration regardless of the use. , to provide a one-chip microcomputer that can effectively utilize program assets.

[Means for Solving the Problems] The one-chip microcomputer of the present invention has: a) an instruction storage device that stores instructions and the like and whose capacity can be changed depending on the purpose; and 1)) a storage device that stores data to be processed.・A data storage device that is used for extended storage and whose capacity varies depending on the purpose; C) A group of peripheral devices whose main purpose is to exchange data and control signals with external devices and whose configuration differs depending on the purpose; d) an instruction holding device that temporarily holds the output of the instruction storage device, an instruction decoding device that decodes the output of the instruction holding device and generates various control signals, and performs numerical operations and logical operations using the control signals. A numerical logic operation device, a timing generator that inputs clocks from the peripherals and generates various timings necessary for computer operation, a general-purpose storage device that temporarily holds data to be processed, and an instruction storage device that specifies the address. e) a core CPU configured by an instruction address indicating device for specifying the address of the data storage device, and a data address specifying device for specifying the address of the data storage device, the configuration of which is fixed regardless of the purpose; shall be.

[Example] A block diagram of the present invention is shown in FIG.

Reference numeral 101 denotes an instruction storage device in which the operating order of the microcombi top and bottom is stored as instructions.

An address (@) where an instruction is stored is specified from the core CPU 102 through an instruction address bus 106, and the instruction is output from that address as an instruction output 109. The instruction output 109 is the core CPU 10
2 and determines the operation of the core CPU. moreover,
A peripheral control signal 108 such as instruction read timing is input from the core CPUIO 2 to the instruction storage device 101 . The peripheral control signal 108 also includes a precharge signal and the like when the instruction storage device 101 is configured with a dynamic circuit. Further, the amount of instructions that the instruction storage device can store, that is, its capacity, can be freely varied depending on the application in which the one-chip microcomputer of the present invention is used.

103 is a data storage device for storing data processed by the one-chip microcomputer of the present invention;
From U102, through the data address bus 107,
Either an address where data is stored is specified and the data is read out from that address onto the 105 data bus, or an address where data is to be stored is specified through the +07 data address bus, and the data is read out from that address. is written. Furthermore, core CP110
2, a peripheral control signal 108 that controls the timing of writing or reading data in the data storage device is input to the data recording/typing device 103. Also, data record 1
The storage capacity of the device, that is, the capacity, can be freely set depending on the purpose for which the one-chip microcomputer of the present invention is used.

104 includes an oscillation device, a timer that counts signals output from the oscillation device, an input device that allows input from an external device, an output device that drives the external device or outputs a control signal, and an external device. Holds the input and output of
Input/output devices, event counters that count external events, control devices that determine the operating status of peripheral devices,
This is a group of peripheral devices including a power supply voltage detection device that detects the power supply voltage, a voltage generation device that generates various voltages from the power supply voltage, etc., and is controlled including timing by a peripheral control signal 108 from the core CPU 102. Core CPU1
The exchange of processing data between 02 and the peripheral device group 104 is as follows:
This is done through data bus 105. Further, a clock 110 is input from the peripheral device group 104 to the core CPU 102 as a system clock of the core CPU 102 .

A detailed block diagram of the core CPU 102 is shown in FIG. 2
Reference numeral 14 indicates various timing signals necessary for the operation of this one-chip microcomputer, such as read timing of the instruction storage device, write or read timing of the data storage device, general purpose storage device 205, numerical logic operation device 204, and instructions. This is a timing generation device that generates the human output timing of the address instruction device 206 and the data address instruction device 203, and inputs the clock 213 (the same signal as the clock 110 in FIG. 1) from the peripheral device group, and as described above. Various timing signals 215
occurs.

The instruction holding device 201 is a device that temporarily holds the instruction output 210 (the same signal as the instruction output 109 in FIG. 1), which is the output of the instruction storage device, for the time necessary to execute the instruction. It is a storage device composed of bits, and all or some of the bits are output to the data bus 207.

The instruction decoding device 202 is a device that decodes the output of the instruction holding device and generates various control signals.
12 (same signal as peripheral control signal 108 in FIG. 1)
and generates an internal control signal 211 that controls the inside of the core CPU. These control signals are the timing signal 21
The peripheral control signal 212 may be a control signal that logically includes 5 or may be a control signal that temporally corresponds to a change in the output of the command holding device. However, the peripheral control signal 212 may be
A control signal that logically includes the timing signal 215 is desirable from the viewpoint of reducing the number of signal lines in a one-chip micro convenience store.

A general-purpose storage device 205 temporarily holds data to be processed by the core CPU, and can freely exchange data with the data bus 207. The purpose of the present invention is to temporarily hold the output of the numerical logic operation unit 204, and to temporarily hold data to be processed without using a data storage device in order to speed up the processing speed. Further, normally there are a plurality of words, but depending on the case, it may be one word, or there may be no word if the numerical logic operation unit 204 has a storage device for holding the operation results.

204 is a numerical logic operation device that performs numerical operations and logical operations on data to be processed in series or parallel depending on the internal control signal 211. For example, the operations that can be processed include the four arithmetic operations in the case of numerical operations, and the logical operations include product, sum, exclusive OR, left/right rotation, and comparison. Numerical logic operation device 20
4 may include a dedicated device for temporarily holding the results, and may also include a data bus 20 for input.
In order to use 7 in a time-sharing manner, temporary storage of input data 1.
It may also include a device.

Reference numeral 206 denotes an instruction address designation device that specifies the address of the instruction storage device, and is usually composed of a plurality of bits of memory device, and is connected to the instruction address bus 208 (the same signal as the instruction address bus 106 in FIG. 1). Outputs the instruction storage address. For example, if the program counter automatically increments the specified address by one each time the execution of an instruction ends, or if the instruction specifies the next address, that address is transferred from the instruction holding device to the deku bus. 2
07, a storage device that holds the address and indicates the address of the instruction storage device. It also has a branching function that reads data from the normal data bus 207 and branches to an instruction address corresponding to the data.

Reference numeral 203 denotes a data address designation device for instructing the address of a data storage device, which usually consists of a multi-bit storage device, and is connected to a data address bus 209 (same signal as the data address bus lO7 in FIG. 1) to indicate the address of the data storage device. Outputs the address of. It reads data from the data bus 207 and indicates the address of the data storage device corresponding to the data. An example is a system having multiple words of storage and switching between them by command to enable multiple addressing.

The core CPU 216 of the present invention has the above configuration, and this configuration is the same regardless of the purpose in which this one-chip microcomputer is used, and the core CPU 216 has the same configuration in terms of chip layout. The parts will be exactly the same. If the application is different, the instruction storage device, data storage device, and peripheral device group can be changed.

[Effects of the Invention] As described above, according to the invention, the configuration of a one-chip microcomputer includes a core CPU that is the same regardless of the purpose, and an instruction storage device, a data storage device, and peripheral devices that change depending on the purpose. By configuring it from groups, it is possible to shorten the development period for various uses, and
This has the effect of making it possible to effectively utilize the developed application program assets.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of the present invention. FIG. 2 is a core CPU configuration diagram of the present invention. 1, 04 instruction storage device Core CPU data storage device Shuhen equipment group data bus instruction address bus data address bus Peripheral side (wholesale signal command output clock instruction holding device ・Instruction decoding device ・Data address instruction device ・Numerical logic operation device ・General-purpose storage device ・Instruction address indicating device ・Data bus ・Instruction address bus ・Data address bus ・Instruction output ・Internal control signal ・Peripheral control signal ·clock ・Timing generator ・Timing signal ・Core CPU Below Up Applicant: Seiko Epson Corporation

Claims (1)

[Claims] (1) In a one-chip microcomputer, there are a) an instruction storage device that stores instructions, etc., and whose capacity is varied depending on the purpose, and b) a storage device that stores data, etc. to be processed, and whose capacity is varied according to the purpose. c) a group of peripheral devices whose main purpose is to exchange data and control signals with external devices and whose configurations differ depending on the purpose; and d) an instruction that temporarily holds the output of the instruction storage device. A holding device, an instruction decoding device that decodes the output of the instruction holding device and generates various control signals, a numerical logic operation device that performs numerical and logical operations based on the control signals, and a computer that inputs a clock from the peripheral. a timing generator that generates various timings necessary for the operation of the system, a general-purpose storage device that temporarily holds data to be processed, an instruction address indicating device that specifies the address of the instruction storage device, and an instruction address instruction device that specifies the address of the data storage device. 1. A one-chip microcomputer comprising: (e) a core CPU configured by a data address instruction device and whose configuration is fixed regardless of the application;