JPH02190020A - Digital signal waveform controller - Google Patents

Abstract

PURPOSE:To generate a pulse signal with a prescribed amplitude and an offset voltage by superimposing a DC component based on a DC component setting voltage on a digital signal set by an amplitude variable circuit and controlling the offset voltage and the amplitude set to the set offset voltage and amplitude. CONSTITUTION:A DC component superimposing voltage generating circuit 11 receives a desired offset voltage, amplitude information and a mark rate information of a pulse pattern outputted from a digital signal source 5 and generates a DC superimposing setting voltage to be a digital signal with an offset voltage having a desired offset voltage and amplitude. A DC component superimposing voltage generating circuit 12 superimposes a pulse signal from an amplitude variable circuit 6 on a DC component generated from the DC component superimposing voltage generating circuit 12, outputs a digital signal with an offset voltage having a set offset voltage and amplitude and latches a value set always with the offset voltage and amplitude. Thus, the a digital signal with an offset voltage having a set offset voltage and amplitude is always generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal generator, particularly one that controls the amplitude and offset voltage of high-speed and ultra-high-speed digital pulses, and relates to a pulse pattern and an offset voltage of an output digital signal. The present invention relates to a digital signal waveform control device in which set amplitude and offset voltage are always maintained even if load conditions on the output side change.

[Conventional technology]

-C, the pulse pattern generator has a circuit configuration in which the polarity, amplitude, and DC component of the generated digital pulses, that is, the offset voltage, can be set as desired, and can meet the various usage requirements of customers.

As a conventional digital signal waveform control device that can arbitrarily and independently set the amplitude and offset voltage of high-speed or ultra-high-speed digital signals, the final output stage of a pulse pattern generator is used as shown in Fig. 10. FET)
By using the transistor 1, the amplitude (VA in FIG. 11) is varied by changing the source potential Vs of the FET+- transistor 1, and by superimposing a DC component on the drain side of the FET- transistor 1 with the choke coil 2. A constant current control circuit that can arbitrarily variably control the offset voltage (V in FIG. 11) was used. In addition, in Figure 10, 3
is a constant current source, and 4 is a capacitor.

(Problem to be solved by the invention) However, the final stage FET as shown in FIG.
The digital signal waveform control device that controls the voltage and current of the L-transistor 1 is basically a constant current control, so depending on the value of the load impedance required for use or the difference in the terminal voltage of the load, Amplitude of output signal■,
and offset voltage ■. There was a drawback that it changed.

In other words, FIG. 12 shows a circuit configuration that models a conventional pulse pattern generator. When the termination conditions differ depending on the type of 13 and 14, the DC voltage at point A in FIGS. 13 and 14 is no longer constant, and the DC component superimposed on the pulse signal output from the variable amplitude circuit 6 changes. there were. Note that in FIGS. 12 to 14, 7 represents a constant current source, and 9 represents a pulse pattern generator.

Further, the DC resistance bone 10 of the choke coil 2 also changes depending on the temperature, and the voltage at point A does not become 'r' due to the temperature change, which has the drawback that the DC component of the pulse signal output from the pulse pattern generator 9 changes. there were.

The present invention is aimed at solving the above-mentioned drawbacks, and has the purpose of solving the above-mentioned drawbacks. Another object of the present invention is to provide a digital signal waveform control device that can always generate a pulse signal with a set constant amplitude and offset voltage even if the polarity of the pulse pattern is set to be reversed.

[Means to solve the problem]

In order to achieve the above object, a digital signal waveform control device of the present invention generates a digital signal with an offset voltage in which a DC component is superimposed on a digital signal. Based on the offset voltage value information to be set, the amplitude value information which is arbitrarily set variably, and the mark rate information of the output pattern, the DC component superimposition setting voltage to be superimposed on the digital signal is determined and the DC component is superimposed. a DC superimposed voltage generation circuit that outputs a set voltage; an amplitude variable circuit that varies the amplitude of the digital signal according to the set amplitude value information; and a variable amplitude circuit that changes the amplitude to the set amplitude value. The DC component outputted based on the DC component superimposed combined pressure from the DC component superimposed voltage generation circuit is superimposed on the digital signal that is being applied, and the DC component and its amplitude of the digital signal with offset voltage at the output end are set. and a DC component superimposed voltage circuit that controls the offset voltage value and amplitude value.

The DC component superposition constant voltage circuit includes a DC component multiplex circuit connected in parallel to the digital signal source, and a digital signal with an offset voltage that is superimposed on the digital signal from the digital signal source via the DC component multiplex circuit. An output voltage detection circuit that detects a DC average value, and a comparison and amplification of the detected voltage detected by the output voltage detection circuit and a DC component superimposed set voltage output from the DC component superimposed voltage generation circuit. A configuration may also be provided including a comparison amplification for applying the voltage obtained to the DC superimposing circuit.

Further, the DC component superimposing constant voltage circuit includes a DC component multiplexing circuit connected in parallel to a digital signal source, a dummy circuit connected in series to the DC component multiplexing circuit, and a potential difference for detecting a dummy voltage of the dummy circuit. A detection circuit compares and amplifies the dummy voltage detected by the potential difference detection circuit and the DC component superimposition setting voltage output from the DC component superimposition voltage generation circuit, and applies the compared and amplified voltage to the DC component superimposition circuit. It is also possible to have a configuration including a comparison amplifier that provides.

Regarding the mark rate information, a mark rate detection circuit that detects the mark rate from the digital signal output from the digital signal source may be provided to obtain the mark rate information to the DC component superimposed voltage generation circuit. can.

Furthermore, regarding the mark rate information, a control device is provided which controls the digital signal source and generates an output digital signal at a predetermined mark rate, and the mark rate information of the generated digital signal is transmitted from the control device to the DC component. It can also be configured to be input to a superimposed voltage generation circuit.

An embodiment of the present invention will be described below with reference to the drawings.

Embodiment C] FIG. 1 is a basic configuration diagram of an embodiment of a digital signal waveform control device according to the present invention, FIG. 2 is a basic configuration diagram of an embodiment of a DC component superimposed voltage circuit, and FIG. 3 is a specific diagram thereof. Embodiment configuration, FIG. 4 is a basic configuration diagram of another embodiment of the DC component superimposed constant voltage circuit,
FIG. 5 shows the configuration of a specific embodiment thereof, FIG. 6 shows the configuration of one embodiment of the DC component superimposed voltage generation circuit, FIG. 7 shows the configuration of one embodiment of the digital signal waveform control device according to the present invention, and FIG. 8 (1
) to IV) are explanatory diagrams of generated waveforms of the DC component superimposed setting voltage, and FIG. 9 is a diagram showing the configuration of another embodiment of the digital signal waveform control device according to the present invention.

In the basic configuration diagram of an embodiment of the digital signal waveform control device according to the present invention shown in FIG. 1, 5, 6, and 8 correspond to those in FIG. 12, 11 is a DC component superimposed voltage generation circuit, and 12 is a DC component 13 is an output end of the superimposed constant voltage circuit.

The DC component superimposed voltage generation circuit 1 includes desired offset voltage W value information and desired amplitude value information set from the outside,
In the pulse pattern of the digital signal to be outputted to the output terminal 13 by receiving the mark rate information of the pulse pattern output from the digital signal source 5, the digital signal with an offset voltage having the set desired offset voltage and amplitude is applied. This is a circuit section that generates a theoretical DC superimposed setting voltage that should become a signal. Here, the offset voltage normal year is indicated by ■ shown in FIG. It refers to the amplitude, and the amplitude refers to ■E.

Further, the mark ratio refers to the percentage of the pulse having the amplitude VA (the shaded portion in FIG. 11) to the pulse signal train. Note that the offset voltage can also refer to Vlo in FIG. 11, but in the present invention, it is Vlo of the 11th level of the pulse signal. This will be explained below.

■ These offset voltages. As mentioned above, the amplitude v7 can be set arbitrarily from the evening panel surface (not shown), and the set value is used as offset voltage value information and amplitude value information to determine the DC superimposed voltage. Generation circuit 1
1 is entered.

The DC component superimposed voltage constant voltage circuit 12 outputs a theoretical voltage based on the pulse signal from the amplitude variable circuit 6 and the offset/voltage value information, amplitude value information, and mark rate information from the DC component superimposed voltage generation circuit 11. The receiver superimposes the DC component superimposed set voltage with the DC component created by the DC component superimposed constant voltage circuit 12, outputs a digital signal with an offset voltage having a set offset voltage and amplitude, and outputs a digital signal with an offset voltage having a set offset voltage and amplitude. 8 and its termination conditions change, or even if the mark rate of the pulse pattern output from the digital signal source 5 changes, the pulse pattern output to the output terminal 13, that is, the offset voltage of the digital signal with offset voltage. and amplitude are always held at the set values.

Next, an embodiment of the DC component superimposed constant voltage circuit 12 will be described.

Figure 2 shows a basic configuration diagram of an embodiment of the DC component superimposed voltage constant circuit, and 5.6.8 corresponds to that in Figure 12, and 1
2.13 corresponds to that of FIG.

14 is a DC superimposing circuit, and 15 is an output voltage detection circuit 16 is a comparison amplifier.

Since the DC superimposition circuit 14 and the output voltage detection circuit 15 are connected to the line of the digital signal source 5 system, they tend to have a large influence on the waveform of the ultra-high speed or high-speed pulse signal generated from the digital signal source 5. The pulse signal generated from the digital signal source 5, which has a small degree of influence, is amplified or attenuated by the amplitude variable circuit 6 so as to have the amplitude VA set from outside. As the variable amplitude circuit 6, a DC amplifier or the like is used that can obtain an amplitude value (2) set with reference to the L level or H level of the pulse signal generated from the digital signal source 5. The pulse signal from the digital signal source 5 that has reached a predetermined amplitude value in this amplitude variable circuit 6 is superimposed with the DC component supplied from the DC component superimposition circuit 14, The output terminal 13 becomes a pulse signal with an offset voltage of offset voltage ■o.
A pulse signal with a desired offset voltage is applied to the load 8.

The output voltage detection circuit 15 detects the DC average value of the offset 1-voltage pulse signal at point A, and feeds back the detected G ratio voltage to the comparator amplifier. The detection voltage and the DC component superimposition setting voltage that determines the DC component of the pulse signal with offset voltage outputted from the output terminal 13, that is, the DC component superimposed voltage generation circuit 11 shown in FIG. The comparator amplifier 16 compares the outputted DC component superimposition set voltage, and the DC voltage is supplied from the comparator amplifier 16 to the DC component superimposition circuit 14 so that the voltage between the two becomes the voltage. A DC component is superimposed on the pulse signal from the variable amplitude circuit 6 at point A via 14.

Therefore, by setting a sufficient gain of the comparator amplifier 16,
Feedback Y from the output voltage detection circuit 15 increases, and when looking at the DC component superimposition circuit 14 and output voltage detection circuit 15 side from point A, it is regarded as a constant voltage source, and the voltage at point A is reduced to zero DC supply. voltage.

Therefore, even if the load 8 and its termination conditions change, the output terminal 1
Offset voltage ■ of the pulse signal with offset voltage output from 3. is maintained at a constant voltage according to the voltage set externally.

Further, as is clear from the above explanation, it goes without saying that the DC component of the pulse signal with offset voltage output from the output terminal 3 changes in accordance with the change in the DC component superimposed setting voltage input to the comparison amplifier 16. . Therefore, even if the polarity of the pulse pattern generated from the DC component superimposed constant voltage circuit 12 is switched, feedback within the DC component superposed constant voltage circuit 12 is applied, and the offset voltage of the pulse signal with offset voltage output from the output terminal 13 is , the set voltage is set externally, and even if the load 8 and its termination conditions change, the set voltage is always maintained.

FIG. 3 shows a specific example configuration of FIG. 2, in which the DC superimposing circuit 14 and the output voltage detection circuit 15 of FIG. 2 are constructed with the same choke coils 17 and 18.

The choke coils 17 and 18 have a high impedance to high frequencies, and the choke coils 17 and 18 have a number of turns that provides such high impedance. Therefore, the choke coils 17 and 18 block the pulse signal from the digital signal source 5 at high frequency, and all the energy of the pulse signal is applied to the load 8 via the connection point indicated by point A. . These choke coils 1
In place of 7.18, pulse signals can be blocked at high frequency.
For example, it is also possible to use a high frequency resistor.

It goes without saying that the impedance of the choke coil 18 is selected to be sufficiently higher than the impedance of the load 8 and lower than the impedance of the comparison amplifier 16.

Note that even if the DC resistance of the choke coil 17 changes due to temperature changes, etc., the DC resistance at point A is maintained at a constant voltage because negative feedback is applied.

Since the operation in FIG. 3 is similar to that in FIG. 2, its explanation will be omitted.

FIG. 4 shows a basic configuration diagram of another embodiment of the DC component superimposed voltage constant circuit, and 5, 6.8 correspond to those in FIG. 12,
12 and 13 correspond to those in FIG. 1, and 14 correspond to those in FIG.

Similar to the one shown in FIG. 2, the DC component superimposing circuit 14 uses an element having high impedance for the ultra-high speed or high-speed pulse signal generated from the digital signal source 5. In the configuration shown in FIG. 4, only the DC component superimposing circuit 14 for superimposing a DC component on the pulse signal is connected, and in the configuration shown in FIG. 2, an output voltage detection circuit I5 is further connected to the pulse signal line. It has a configuration that has less influence on the pulse signal compared to the .

The dummy circuit 19 is connected in series with the DC superimposing circuit 14 and connected to the comparison amplifier 21, so that the direct current flowing through the dummy circuit 19 is connected to the DC superimposing circuit 14.
Flows into 4. Therefore, even if the termination conditions change depending on the type of load 8, the DC current flowing through the dummy circuit 19 and the DC superimposing circuit 14 remains the same.

Now, from a DC point of view, the DC resistance value Z of the DC component superimposing circuit 14
If I and the DC resistance value Z2 of the dummy circuit 19 are selected to be the same, that is, if the same elements are used, the voltage drop between points A and B and between points B and C will be the same, and changes due to temperature and current will be the same. will be the same. In other words, the voltage drop of the DC superimposing circuit 14 is projected onto the dummy circuit 19. Potential difference detection circuit 20
detects the voltage drop of the dummy circuit 19, and adds the detected voltage to the above-mentioned DC component superimposed set voltage in the adder circuit 22,
The added voltage and the output voltage of the dummy circuit 19, that is, point B
The comparison amplifier 21 compares and amplifies the voltage so that the difference between the two voltages becomes zero, and the comparatively amplified voltage is applied to the dummy circuit 19. Therefore, even if the termination conditions change depending on the type of load 8 or the temperature changes, the voltage at point B will always be high by the voltage drop caused by the DC superimposing circuit 14, and the voltage at point B will remain high from the output terminal 13. Offset voltage of the pulse signal with offset voltage that is output ■. is held constant.

On the other hand, if the DC resistance value Z1 of the DC component superimposing circuit 14 and the DC resistance (a!Zz) of the dummy circuit 19 are different, the voltage drop between points A and B and between points B and C is In order to ensure that the voltage at point B is always the same even if the current or temperature environment changes, the detected voltage of the potential difference detection circuit 20 is compensated and positive feedback is applied to the point B so that the voltage at point B is determined by the DC component superimposition circuit I4. It is controlled so that it is always high by the voltage drop.

In FIG. 4, the comparator amplifier 21 applies feedback from point B, but it can also be configured to apply feedback from point C, as shown by the dotted line.

In this case, point C becomes a constant voltage source, and point B becomes a constant voltage source.''Compared to the case of two legs, twice the voltage drop occurs between the DC superimposing circuit 14 and the dummy circuit 19, and therefore the potential difference detection circuit 20 It is necessary to double the detection voltage and apply positive feedback. Other than doubling this amount of feedback, it is the same as the above explanation, and the voltage at point C is increased by the voltage at point A, which is the sum of the voltage drop caused by the DC superimposing circuit 14 and the voltage drop caused by the dummy circuit 19. controlled to be higher.

FIG. 5 shows a specific example configuration of FIG. 4, and depicts an example in which choke coils are used in the DC superimposing circuit 14 and the dummy circuit 19.

DC resistance value Z of the choke coil of the DC component superimposing circuit 14,
and the DC resistance value Z2 of the choke coil of the dummy circuit 19 are equal, and the resistance value remains 2.0 even against changes in the environment such as current and temperature. , -22, that is, when the same choke coil is used, the detection voltage detected by the potential difference detection circuit 20 is positively fed back to the addition circuit 220 point E with a gain of 1.

Other embodiments include the following.

That is, the choke coil of the DC superimposing circuit 14 and the dummy circuit 19
2. The DC resistance values Z3 and Z2 of the choke coils are the same. =
2. When the temperature changes are different, the potential difference detection circuit 20 is configured with elements whose gain is 1 and whose temperature changes are the same.

If the DC resistance values Z1, Z, of each choke coil in the DC component superimposing circuit 14 and the dummy circuit 19 are different (Z, ~Z-1), and the temperature changes are the same, the gain of the potential difference detection circuit 20 is changed and the DC component superimposing circuit The same voltage as the voltage drop of the circuit 14 is fed back positively.

If the DC resistance value C+L of each choke coil in the DC component superimposing circuit 14 and the dummy circuit 19 is different (ZINZ2) and the temperature changes are also different, the potential difference detection circuit 20 is configured with elements whose temperature changes are the same, and the DC component superimposing circuit 14 and the dummy circuit 19 are The gain of the potential difference detection circuit 20 is determined so that the same voltage as the voltage drop of the circuit 14 is fed back.

Note that, as shown by the dotted line in FIG. 4, when the feedback position of the comparator amplifier 21 is taken from point C, the detection voltage detected by the potential difference detection circuit 20 is Needless to say, it is necessary to double the amount and return it.

Although choke coils are used as examples of the DC superimposing circuit 14 and the dummy circuit 19, they can also be replaced with high-frequency resistors.

The DC component superimposition constant voltage circuit 12 performs the operation as described above.
Therefore, if the mark rate of the pulse pattern generated from the digital signal source 5 is known in advance, or if the mark rate information of the pulse pattern is obtained by detecting the mark rate, the mark rate can be determined by some means. When the mark rate information is known, it is possible to generate a DC superimposed setting voltage from the DC superimposed setting voltage generation circuit 11 to the DC superimposed constant voltage circuit 12, and even if the mark rate changes, that is, the digital Even if a change occurs in the pulse pattern output from the signal source 5,
Furthermore, even if the termination conditions change depending on the type of load 8, the offset voltage (2) shown in FIG. 11 of the digital signal with offset voltage output to the output terminal 13.

And its amplitude (1) can always be kept constant at each point set from the external panel surface.

Offset voltage value information set arbitrarily from the external panel surface, amplitude value information, and mark rate information obtained by any of the above means are input, and a DC component superimposed constant voltage circuit is created based on these three pieces of information. As a method of generating the above-mentioned DC component superimposed setting voltage that is output to 12, a calculation method, a method of reading out the DC component superimposed setting voltage stored in the memory in advance based on these three pieces of information, etc. are used. It will be done.

FIG. 6 shows an embodiment of the configuration of a DC component superimposed voltage generating circuit, which is a method for generating a DC component superimposed set voltage from a memory.

11 corresponds to that in FIG. 1, 25 to 27 are analog-to-digital converters, 28 is an address generation circuit, and 29
30 represents a memory, and 30 represents a digital-to-analog converter.

Offset voltage value information and amplitude information set from an external panel and mark rate information obtained by some means as described above are input to the analog-digital converters 25 to 27, and each piece of information is input. Digitized. If any of these three pieces of information is already digitized, the corresponding analog-to-digital converters 25 to 27 are not required.

The three pieces of information digitized by the analog-to-digital converters 25 to 27 are input to an address generation circuit 28, where they are converted into addresses for accessing the memory 29.

In the memory 29, various combinations of the above-mentioned three information values, that is, information data of the DC component superimposed setting voltage for each individual, with the offset voltage value information, amplitude value information, and mark rate situation as parameters, are stored in advance at predetermined addresses. has been done. The information data of the DC component superimposed set voltage stored in advance in this memory 29 may be obtained by experiment or by calculation.

By accessing the memory 29 with the address generated from the address generation circuit 28, it corresponds to the offset voltage value information, amplitude value information, and mark rate information input from the memory 29 to the DC component superimposed setting voltage generation circuit 11. Information data of the DC component superimposed setting voltage is read. The information data of the DC component superimposed setting voltage read from the memory 29 is converted into an analog by the digital-to-analog converter 30 and outputted from the DC component superimposed setting voltage generation circuit 11 as a DC component superimposed setting voltage.

FIG. 7 shows the configuration of an embodiment of a digital signal waveform control device according to the present invention, and 5. 6. 8 corresponds to that in FIG. 12, and 11 to 13 correspond to those in FIG. 31 is a mark rate detection circuit, 32 and 33 are digital-to-analog converters, 34 is an analog multiplier, and 35 is an adder.

The mark rate detection circuit 31 detects the mark rate of the pulse pattern generated from the digital signal source 5, and obtains mark rate information input to the DC component superimposed setting voltage generation circuit 11 shown in FIG. This mark rate information is obtained by a mark rate detection circuit 31 using, for example, a rectifier circuit consisting of a diode and a capacitor or a high frequency resistor.

The output of the pulse pattern generated from the digital signal source 5 is the DC average value (■) of the pulse signal train. . ,=(VAS V
AsXMs)=Vas(Ms 1 ).

VAS is the amplitude of the pulse signal generated from the digital signal source 5, and Ms is the mark rate (0≦Ms≦1).

An analog signal containing mark rate information obtained from the mark rate detection circuit 31 is multiplied by an analog signal of amplitude value information converted into an analog via a digital-to-analog converter 33 in an analog multiplier 34 . If the analog signal of the amplitude value information converted into analog via the digital-to-analog converter 33 is represented by ■, then the output SA of the analog multiplier 34
is 5A=KxVa xVocs=KXVaXVAs(M
s・1). K is the gain of the analog multiplier 34, and if K=1/VAs is chosen, 5A=VA (M, -1)
becomes. This situation is shown in FIG. 8 (II).

The output SA of the analog multiplier 34 and the offset voltage value signal S converted into an analog by the digital-to-analog converter 32
. (shown in FIG. 8 (III)) are added by the adder 35.

S of the adder 35 is S s = S o + S
A=S o + V sX(M!-1). That is, the DC component superimposed set voltage shown in FIG. 8 (IV) is obtained.

The output Ss of the adder 35 is input to the DC component superimposed constant voltage circuit 12.

The theoretical value of the DC average value to be outputted to the output terminal 13 from the DC component superimposed setting voltage generation circuit 11, that is, the above-mentioned DC component superimposed setting voltage, is changed depending on the change in the pulse pattern generated from the digital signal source 5. That is, the DC component superimposition constant voltage circuit 12 changes in accordance with the change in the value of the mark rate information, and based on the DC component superimposition setting voltage, the DC component superimposition constant voltage circuit 12 always holds the digital signal with an offset voltage output to the output terminal 13 constant. It works like this. This DC superimposed constant voltage circuit 12
Since the circuit configuration explained in Figs. ■ Offset voltage set from. and amplitude VA are maintained as set.

The amplitude value information is also input to the amplitude variable circuit 6, and the amplitude of the pulse is changed by the amplitude variable circuit 6 in accordance with changes in the amplitude value information. For example, when a DC amplifier is used as the variable amplitude circuit 6, its gain changes in accordance with changes in amplitude value information to generate desired amplitude values V. Furthermore, as described above, the variable amplitude circuit 6 may be one that can obtain the amplitude value (■) set based on the level (or 1 level) of the pulse signal generated from the digital signal source 5. Needless to say.

FIG. 9 shows the configuration of another embodiment of the digital signal waveform control device according to the present invention, 5.6.8 corresponds to that in FIG. 12, and 11 to 13 correspond to that in FIG. 1. death,
32 to 35 correspond to those in FIG. 36
37 represents a CPU and a digital-to-analog converter.

In FIG. 9, the mark rate information shown in FIG. 1 is input from the CPU 36, and the CPU 36 controls the generation of the pulse pattern from the digital signal source 5. . In other words, the pulse pattern generated from the digital signal arts is
36 instructions, and therefore the CPU
At 36, the mark rate of the pulse pattern generated from the digital signal source 5 is known. This known mark rate information is sent from the CP tJ36 to the DC component superimposition setting voltage generating circuit 11, and is converted into an analog signal by the digital-to-analog converter 37. Since the operation is the same as that in FIG. 8, the explanation of the operation will be omitted.

In FIGS. 8 and 9, the DC component superimposed setting voltage is generated in the DC component setting voltage generation circuit 11 using an analog signal, but as shown in FIG. 6, it is processed using a digital signal. At the time of the final output, it may be converted into an analog signal using a digital-to-analog converter to generate a DC component superimposed setting voltage.

At this time, analog multiplier 34 and adder 35 are of digital type.

It goes without saying that the DC superimposed voltage generating circuit 11 shown in FIG. 6 may be used instead of the DC superimposed voltage generating circuit 11 shown in FIGS. 7 and 9.

In the above explanation, offset voltage ■. can be seen in Figure 11.

〔Effect of the invention〕

As explained above, according to the present invention, since constant voltage control is used, the set offset voltage is maintained even if the type of load, that is, the impedance of the load changes, or even if the termination conditions change. , it is possible to always apply a correct digital signal with offset voltage to the load.

In addition, the mark rate information is input to the DC component superimposed voltage generation circuit to control the digital signal with offset voltage, so even if the mark rate of the pulse pattern generated from the digital signal source changes, the set A digital signal with an offset voltage whose offset voltage and amplitude are maintained can be generated at all times, eliminating the inconvenience of having to reset the settings.

Even if the polarity of the pulse signal is reversed, the DC component superimposed voltage generation circuit generates the corresponding DC)lltl superimposed setting voltage. This is extremely useful when a digital signal is available and requires forward/reverse inversion.

In the case of claim 3, since the number of circuits connected to the digital signal source is reduced, the influence on the signal waveform is reduced, and a pulse signal with a good waveform can be output.

[Brief explanation of the drawing]

Figure 1 is a basic configuration diagram of an embodiment of a digital signal waveform control device according to the present invention, Figure 2 is a basic configuration diagram of an embodiment of a DC component superimposed constant voltage circuit, and Figure 3 is a detailed configuration diagram of an embodiment thereof. ,
FIG. 4 is a basic configuration diagram of another embodiment of the DC component superimposed voltage constant voltage circuit, FIG. 5 is the configuration of one specific embodiment thereof, FIG. 6 is the configuration of one embodiment of the DC component superimposed voltage generating circuit, and FIG. 7 FIG. 8 shows the configuration of an embodiment of the digital signal waveform control device according to the present invention.
1) or IV) is an explanatory diagram of the generated waveform of the DC component superimposed setting voltage, FIG. 9 is a configuration of another embodiment of the digital signal waveform control device according to the present invention, and FIG. 10 is a diagram showing the configuration of a conventional digital signal waveform control device. The final stage configuration diagram, Figure 11 is a signal explanation diagram of a digital signal with offset voltage, Figure 12 is a model circuit diagram of a conventional pulse pattern generator, Figures 13 and 14.
The figure is an explanatory diagram of the terminal end of a load connected to a pulse pattern generator. In the figure, 1 is a transistor (FET), 2 is a choke coil,
3 is a constant current source, 4 is a capacitor, 5 is a digital signal source, 6 is a variable amplitude circuit, 7 is a constant current source, 8 is a load, 9 is a pulse pattern generator, 11 is a DC component superimposed voltage generation circuit,
12 is a DC component superimposing constant voltage circuit, 13 is an output terminal, 14 is a DC component multiplexing circuit, 15 is an output detection circuit, 16 is a comparison amplifier, 17.18 is a choke coil, 19 is a dummy circuit, 2
0 is a potential difference detection circuit, 21 is a comparison amplifier, 22 is an addition circuit, 25, 26, 27 is an analog-digital converter,
28 is an address generation circuit, 29 is a memory, 30 is a digital-to-analog converter 30, 31 is a mark rate detection circuit,
32 and 33 are digital-to-analog converters, 34 is an analog multiplier, 35 is an adder, 36 is a CPU, and 37 is a digital-to-analog converter. Rod 1 Figure 3 Figure 2 Figure 4 Figure rr Figure 5 Figure 6 Figure 9 Figure 7 Figure 8L-4 (II) Figure 10 Figure 11

Claims (1)

[Scope of Claims] 1. A digital signal waveform control device that generates a digital signal with an offset voltage in which a DC component is superimposed on a digital signal, comprising: offset voltage value information that is arbitrarily set variably for the digital signal; Based on the amplitude value information that is arbitrarily set variably and the mark rate information of the output pattern, the DC component superimposition voltage to be superimposed on the digital signal is determined and the DC component superimposition voltage is output. a generation circuit; an amplitude variable circuit that varies the amplitude of the digital signal according to the set amplitude value information; Superimposes the DC component output based on the DC component superimposition setting voltage from the superimposed voltage generation circuit, and controls the DC component and its amplitude of the digital signal with offset voltage at the output end to the set offset voltage value and amplitude value. A digital signal waveform control device comprising a DC component superimposed constant voltage circuit. 2. The DC component superposition constant voltage circuit includes a DC component multiplex circuit connected in parallel to a digital signal source, and a digital signal with an offset voltage that is superimposed on the digital signal from the digital signal source via the DC component multiplex circuit. an output voltage detection circuit that detects a DC average value of , and compares and amplifies the detected voltage detected by the output voltage detection circuit with a DC component superimposed set voltage output from the DC component superimposed voltage generation circuit, and compares A digital signal waveform control device comprising: a comparison amplifier that applies the amplified voltage to the DC superimposing circuit. 3. The DC part superimposing constant voltage circuit includes a DC part superimposing circuit connected in parallel to a digital signal source, a dummy circuit connected in series to the DC part superimposing circuit, and a potential difference for detecting a dummy voltage of the dummy circuit. A detection circuit compares and amplifies the dummy voltage detected by the potential difference detection circuit and a DC component superimposition setting voltage output from the DC component superimposition voltage generation circuit, and supplies the comparatively amplified voltage to the DC component superimposition circuit. A digital signal waveform control device characterized by comprising a comparison amplifier that gives 4. Claim 1, further comprising: a mark rate detection circuit for detecting the mark rate from the digital signal outputted from the digital signal source, to obtain mark rate information to the DC component superimposed voltage generation circuit. , 2 or 3. The digital signal waveform control device according to any one of . 5. A control device that controls the digital signal source and generates an output digital signal at a predetermined mark rate, and inputs mark rate information of the generated digital signal from the control device to the DC component superimposed voltage generation circuit. 4. The digital signal waveform control device according to claim 1, wherein the digital signal waveform control device is configured to perform the following.