JPH02192371A - Charge-coupled type solid-state image pickup device - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by cascade-connecting plural delay elements in series, and supplying a transfer signal of prescribed cycle to the delay element at an initial stage. CONSTITUTION:The delay element E consists of an inverter circuit, a resistor R connected in series to the input contact of the inverter circuit, and a capacitor C interposed between the input contact of the inverter circuit and a ground contact, and respective delay element is connected in series. When the transfer signal phiin is applied, a first driving signal phi8 exists in the same cycle T, and goes to an inverted rectangular signal. Assuming the signal phi8 as reference, the next driving signal phi7 is delayed by delay time tau decided by the resistor R and the capacitor C, then, goes to an inverted rectangular wave, and following driving signals appear as the rectangular waves in which the time tau are increased and also inverted. Thereby, since the driving signal for vertical transfer is generated only by transferring the delay element having the time tau by the signal phiin, the circuit constitution can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge-coupled solid-state imaging device that transfers signal charges by independently applying drive pulses to vertical charge transfer electrodes.

[Conventional technology]

As a charge-coupled solid-state imaging device that transfers signal charges by applying driving pulses to vertical charge transfer electrodes independently, an accordion CCD (^,
ta1. Proceedings of the I
EEE International Electron
Devices Msetting+ 1984. P
, P., 40-43).

First, to explain the structure of this COD, as shown in FIG.
Shift registers SR, SR, which generate driving signals for driving transfer to the horizontal charge transfer path C via the horizontal charge transfer path C are provided.

That is, in the light receiving area A, a pixel group is a group of photodiodes arranged in the horizontal and vertical directions, and a vertical charge transfer channel is formed adjacent to these pixels and extends in the vertical direction. Transfer electrodes g1 to g formed on the upper surface of the transfer channel shift register SR
, the signal charge is transferred to the storage region B side by supplying a drive signal of a specific timing using an accordion transfer method generated by . In the accumulation region B, a charge transfer channel is formed which is connected to the vertical charge transfer channel of the light receiving region A and whose upper surface is shielded from light. A transfer electrode jt'''Jn is formed to receive a drive signal at a specific timing and transfer the signal charge to the storage region B side.

Although it has a structure similar to that of a so-called frame transfer type charge-coupled solid-state imaging device, this CCD is unique in its signal charge transfer drive method, in which all transfer electrodes have a phase difference. The signal charge is transferred by providing different and independent drive signals.

Next, this driving method will be explained based on FIG. 6. still,
FIG. 6 illustrates a portion An of the n-th channel (shaded portion in FIG. 6) in the light receiving area A shown in FIG. 5 as a representative. FIG. 6(a) shows the timing and waveform of the clock signals V+, Vz for operating the shift register SR, and the transfer signal IM input to the shift register SR.

FIG. 6(b) shows a partial configuration of shift register SR. FIG. 6(c) shows the operation of the signal charge moving through a portion An of the n-th channel according to each drive signal of FIG. 6(a).

The shift register SR+ transfers the transfer signal I in synchronization with the timing signals V, , V, which have the same period and different phases.
It consists of a predetermined number of shift elements that serially shift M, and the structure of each shift element is, for example, the seventh stage.
As shown in Figures (a) and (b), the switching element connected to the input contact of the inverter circuit, and the capacitive element (using junction capacitance, etc.) connected between the input contact and the ground contact of the inverter circuit. The shift elements are connected in series and the switching elements are opened and closed by the clock signal (2) or (2), thereby transmitting the signal IM in synchronization with the clock signal (2), which is generated at the output contact of each inverter circuit. A drive signal φ heavy to φ· is applied to the transfer electrode g+""ge in FIG.

Here, as shown in FIG. 6(a), the drive signal φ8 applied to the transfer electrode g on the side closer to the storage region B is generated earliest (the remaining drive signals are sequentially applied with a quarter period). (T/4)
It is a rectangular signal whose phase is inverted with a delay of .

On the other hand, shift registers SR and S related to storage area B are
It has the same configuration as R, and is configured to transfer the signal charge transferred from the light receiving area A to the horizontal charge transfer path C by a drive signal having the same timing as the drive signals φ1 to φ.

Next, to explain the operation of this CCD, for example, Fig. 6 (
Assuming that the subject is imaged at a time before time 1+ in a), time 1. , optical signal charges are accumulated in potential wells formed at every other electrode in the transfer channel by drive signals φ, .about.φ8 at the voltage levels shown.

Next, at time t2, the signal charge q1 on the most output side is transferred by one pixel, and then from the latter half of time t2, signals qz + q3 + qa are transferred in the order. In this way, since the signal charges are transferred in order starting from the endmost signal charge in the transfer direction, even if the number of transfer electrodes is reduced, it is possible to transfer a plurality of signal charges without mixing them.

After all the signal charges in the light receiving area A are transferred to the storage area B in this way, the storage area B also transfers the signal charges to the horizontal charge transfer path C by performing a similar transfer operation. It should be noted that each time the accumulation region B transfers signal charges for one column in the horizontal scanning direction to the horizontal charge transfer path C, the horizontal charge transfer path C performs a serial transfer operation to output the signal charges to the output terminal OUT.
The storage area B and the horizontal charge transfer path C are synchronized to ensure the operation of the storage area B and the horizontal charge transfer path C.

[Problem to be solved by the invention]

However, in a charge-coupled solid-state imaging device using such a conventional transfer method, the configuration of the shift register is such that the transfer signal IM is synchronized with the clock signals V, , V, as shown in FIG. Since the drive signal is generated by transferring the clock signals, a circuit to generate these two-phase clock signals and wiring to connect the circuit and the shift element are required. There is a problem in that if the circuit is integrated, it becomes large and complicated.

The present invention has been made in view of such problems,
It is an object of the present invention to provide a shift register for an accordion transfer type charge-coupled solid-state imaging device that can obtain desired characteristics with an extremely simple structure.

(Means for Solving the Problems) In order to achieve this object, the present invention connects a plurality of delay elements in series, supplies a transfer signal consisting of a rectangular signal with a predetermined period to the delay element of the first stage, and
The delay time of each delay element is set to a value smaller than half the period of the transfer signal, and the signal output from each delay element is configured to be supplied as a drive signal to a specific associated transfer electrode. do.

[Effect]

In the present invention having such a configuration, a drive signal for vertical transfer is generated simply by transferring the transfer signal through a delay element having a specific delay time.
There is no need for a lock signal as in the conventional case, and the circuit configuration is extremely simple.

〔Example〕

An embodiment of the charge-coupled solid-state imaging device of the present invention will be described below with reference to the drawings. First, to explain the configuration, the overall schematic structure is the same as that shown in FIG. FIG. 1 shows a part of this light-receiving area A in an enlarged manner. In FIG. 1, the electrode openings pH, PI□, PI3
~Pllll+P! 12°P, 3 are formed in an orderly manner, and the electrode openings P, ~P al+ are arranged in the vertical direction.
Pl! ~P st+ P +, l-P 113 between vertical charge transfer channels i, i+1 . i+2 is formed, and the remaining portion (shaded portion) is a channel stop region. Note that the transfer electrodes g1 to g8 form vertical charge transfer channels i, i+1 . It is formed on the top surface of i+2.

D1 to D are delay elements constituting a shift register that generates drive signals φ, to φ8 to be applied to transfer electrodes gl-gs, and each delay element DI"
"D?" have the same delay time τ and are connected in series, and their respective output contacts are connected to the transfer electrodes g1 to g.
, and a transfer signal φ, φ, having a predetermined period is supplied to the initial stage delay element DI, thereby generating drive signals φ, ˜φ, from each of the delay elements DI˜D.

To further explain the configuration of this shift register based on FIG. 2, each delay element (E in the dotted line in FIG. 2 is 1
The delay element shown in FIG. Similarly, the respective delay elements are connected in series. A predetermined delay time τ is set by the time constant of the resistor and the capacitive element, and the inverter circuit is formed by, for example, a CMOS process.

Next, the operation of such a shift register will be explained based on FIG.

The transfer signal φ directly supplied to the first stage delay element is
In the vertical charge transfer channel shown in Fig. 1, the signal charge is transferred in the vertical direction Y by 1 pixel at a period T of "H".
, is a rectangular wave that repeatedly inverts to the "L" level, and when this transfer signal φ table 7 is applied, the first drive signal φ8 has the same period T and becomes an inverted rectangular signal. Based on this drive signal φ, the next drive signal φ becomes an inverted rectangular signal delayed by a delay time determined by the resistance and capacitance, and subsequent drive signals are also sequentially delayed as shown in the figure. Appears as a square wave that increases in time and is inverted. Then, after the signal charges generated in each of the electrode openings pH to pHl shown in FIG. 1 are accumulated in the transfer packets in the charge transfer channels adjacent to them, when the signal charges are transferred by these drive signals, A transfer similar to that described in FIG. 6 can be performed. In the explanation of this embodiment, for convenience of explanation, the case where signal charges of 3 x 8 photodiodes are transferred is explained, but if the number of stages of connection of delay elements is increased, any number of signal charges can be transferred. Needless to say, charge can be transferred.

Further, the present invention can also be applied to a shift register for signal charge transfer of a charge transfer channel provided in the storage section B of FIG.

As described above, according to this embodiment, it is possible to provide a shift register with an extremely simple structure, and furthermore, since the drive signal is not generated according to the clock signal as in the conventional case, high-speed transfer is possible.

Next, another embodiment of the present invention will be described based on FIG. FIG. 4 is shown corresponding to FIG. 1, and the difference in structure is that the transfer signal φi is applied to the left end of transfer electrode g via the inverter circuit 11, and appears at the right end of transfer electrode g8. Transfer the drive signal to the electrode g via the inverter circuit ■2
, is applied to the right end of transfer electrode g, and then the drive signal appearing at the left end of transfer electrode g is passed through the inverter circuit ■ to the next transfer electrode g,
The remaining transfer electrodes g6 onward are also wired in a similar circuit configuration.

With this configuration, it becomes an inverter circuit! Since the transfer electrodes g+-gs are alternately connected in series, the wiring is simplified and the internal resistance and parasitic capacitance of each transfer electrode itself can be reduced to a time constant for setting the delay time τ. At the same time, since the drive signal is directly applied from each transfer electrode, it is possible to use one transfer electrode and one inverter as a set of delay elements, and the circuit scale can be simplified. can do. In this embodiment, the delay time due to the transfer electrode and the transfer signal φ
In order to make the relationship between the period of the transfer signal φ and the period similar to that shown in FIG.

It is desirable to set the cycle appropriately.

In the two embodiments described above, a delay element consisting of an inverter circuit, a resistor, and a capacitive element is applied, and is therefore suitable for manufacturing using semiconductor integrated circuit technology, but the delay element is not limited to these. (
, delay lines having other circuit configurations or passive elements may be used.

In addition, in this embodiment, a frame transfer type CCD was explained, but an interline transfer type CCD
The present invention can be similarly applied to various solid-state imaging devices such as CDs or frame interline transfer type CCDs.

[Effects of the Invention] As explained above, according to the present invention, a plurality of delay elements are connected in series and a transfer signal consisting of a rectangular signal with a predetermined period is supplied to the first stage delay element,
The delay time of each delay element is set to a value smaller than half the period of the transfer signal, and the signal output from each delay element is configured to be supplied as a drive signal to a specific associated transfer electrode. Therefore, the transfer signal transfers the delay element having a specific delay time (as a result, a drive signal to be applied to the vertical transfer tunnel is generated), and the circuit configuration can be extremely simplified.

[Brief explanation of the drawing]

FIG. 1 is a structural explanatory diagram illustrating the structure of an embodiment of the present invention; FIG. 2 is a configuration explanatory diagram showing the configuration of the shift register in FIG. 1; FIG. 3 is a shift register diagram of FIG. A timing chart explaining the operation of the register; Fig. 4 is a structural explanatory diagram showing the structure of another embodiment of the present invention; Fig. 5 is a structural explanatory diagram showing the structure of the conventional example; Fig. 6 is a structural explanatory diagram showing the structure of the conventional example; Explanatory diagram illustrating the configuration and operation timing of shift register; FIG. 7 is a configuration explanatory diagram showing the configuration of a conventional shift register in detail. Codes in the figure: pH~P83; electrode opening g+~gsi transfer electrode D1~D, i delay element 1, i +1+ 1 +2; charge transfer channel R; resistor C; capacitive element ■1~■,: inverter circuit

Claims (1)

[Claims] A plurality of pixels formed in a horizontal scanning direction and a vertical scanning direction;
A vertical charge transfer channel formed adjacent to a pixel group arranged in a vertical scanning direction, a horizontal charge transfer channel connected to the channel, a transfer electrode formed in the vertical charge transfer channel, and these transfer electrodes. In a charge-coupled solid-state imaging device, the charge-coupled solid-state imaging device includes a shift register that supplies drive signals in order from the one closest to the horizontal charge transfer channel to transfer signal charges to the vertical charge transfer channel; , consisting of a plurality of delay elements connected in series, a transfer signal consisting of a rectangular signal with a predetermined period is supplied to the first stage delay element, and the delay time of each delay element is a value smaller than half the period of the transfer signal. A charge-coupled solid-state imaging device, characterized in that the charge-coupled solid-state imaging device is configured to supply a signal output from each delay element as a drive signal to the transfer electrode specifically associated with the drive signal.